| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsExpandPseudo.cpp | 176 BuildMI(sinkMBB, DL, TII->get(Mips::SRLV), Dest) in expandAtomicCmpSwapSubword()
457 BuildMI(sinkMBB, DL, TII->get(Mips::SRLV), Dest) in expandAtomicBinOpSubword()
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| D | MipsScheduleP5600.td | 213 ADDu, SLLV, SRAV, SRLV, LSA, COPY)>;
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| D | MipsInstrInfo.td | 2084 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
2784 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
2790 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
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| /external/v8/src/mips/ |
| D | constants-mips.h | 505 SRLV = ((0U << 3) + 6), enumerator
1284 FunctionFieldToBitNumber(SLLV) | FunctionFieldToBitNumber(SRLV) |
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| D | disasm-mips.cc | 1319 case SRLV: in DecodeTypeRegisterSPECIAL()
|
| /external/v8/src/mips64/ |
| D | constants-mips64.h | 487 SRLV = ((0U << 3) + 6), enumerator
1325 FunctionFieldToBitNumber(SRLV) | FunctionFieldToBitNumber(DSRLV) |
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| D | disasm-mips64.cc | 1493 case SRLV: in DecodeTypeRegisterSPECIAL()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips1/ |
| D | valid.s | 159 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips2/ |
| D | valid.s | 198 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips3/ |
| D | valid.s | 263 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32/ |
| D | valid.s | 261 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_32.c | 401 EMIT_SHIFT(SRL, SRLV); in emit_single_op()
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| D | sljitNativeMIPS_64.c | 495 EMIT_SHIFT(DSRL, DSRL32, SRL, DSRLV, SRLV); in emit_single_op()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32r5/ |
| D | valid.s | 311 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32r3/ |
| D | valid.s | 310 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32r2/ |
| D | valid.s | 310 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64r3/ |
| D | valid.s | 376 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64/ |
| D | valid.s | 342 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64r5/ |
| D | valid.s | 382 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips4/ |
| D | valid.s | 323 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips5/ |
| D | valid.s | 324 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64r2/ |
| D | valid.s | 386 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 768 {DBGFIELD("SRLV") 1, false, false, 1, 2, 1, 1, 0, 0}, // #493
1788 {DBGFIELD("SRLV") 16382, false, false, 0, 0, 0, 0, 0, 0}, // #493
2707 case 493: // SRLV
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 1087 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) in EmitAtomicBinaryPartword()
1296 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) in EmitAtomicCmpSwapPartword()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1771 Opcode = Mips::SRLV; in selectShift()
|