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Searched refs:SRsrc (Results 1 – 4 of 4) sorted by relevance

/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelDAGToDAG.cpp92 bool SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
96 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
99 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
104 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &SOffset,
107 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
109 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
868 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, in SelectMUBUFAddr64() argument
889 SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0); in SelectMUBUFAddr64()
896 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, in SelectMUBUFAddr64() argument
903 return SelectMUBUFAddr64(Addr, SRsrc, VAddr, SOffset, Offset, GLC, SLC, TFE); in SelectMUBUFAddr64()
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DSIInstrInfo.cpp2327 MachineOperand *SRsrc = getNamedOperand(MI, AMDGPU::OpName::srsrc); in legalizeOperands() local
2328 if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg()))) { in legalizeOperands()
2329 unsigned SGPR = readlaneVGPRToSGPR(SRsrc->getReg(), MI, MRI); in legalizeOperands()
2330 SRsrc->setReg(SGPR); in legalizeOperands()
2348 MachineOperand *SRsrc = &MI.getOperand(SRsrcIdx); in legalizeOperands() local
2350 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()), in legalizeOperands()
2360 unsigned SRsrcPtr = buildExtractSubReg(MI, MRI, *SRsrc, in legalizeOperands()
2441 .addOperand(*SRsrc) in legalizeOperands()
2468 .addOperand(*SRsrc) in legalizeOperands()
2486 SRsrc = getNamedOperand(*Addr64, AMDGPU::OpName::srsrc); in legalizeOperands()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelDAGToDAG.cpp119 bool SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
123 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
126 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
133 SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
136 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &SOffset,
139 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
141 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
1055 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, in SelectMUBUFAddr64() argument
1076 SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0); in SelectMUBUFAddr64()
1083 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, in SelectMUBUFAddr64() argument
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DSIInstrInfo.cpp3606 MachineOperand *SRsrc = getNamedOperand(MI, AMDGPU::OpName::srsrc); in legalizeOperands() local
3607 if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg()))) { in legalizeOperands()
3608 unsigned SGPR = readlaneVGPRToSGPR(SRsrc->getReg(), MI, MRI); in legalizeOperands()
3609 SRsrc->setReg(SGPR); in legalizeOperands()
3628 MachineOperand *SRsrc = &MI.getOperand(SRsrcIdx); in legalizeOperands() local
3630 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()), in legalizeOperands()
3640 unsigned SRsrcPtr = buildExtractSubReg(MI, MRI, *SRsrc, in legalizeOperands()
3721 .add(*SRsrc) in legalizeOperands()
3748 .add(*SRsrc) in legalizeOperands()
3766 SRsrc = getNamedOperand(*Addr64, AMDGPU::OpName::srsrc); in legalizeOperands()
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