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Searched refs:SSCG_PLL_CLKE_MASK (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-imx/mx8m/
Dclock.c149 pll_clke = SSCG_PLL_CLKE_MASK; in decode_sscg_pll()
622 val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK | in sscg_pll_init()
637 val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK | in sscg_pll_init()
707 setbits_le32(&ana_pll->sys_pll1_cfg0, SSCG_PLL_CLKE_MASK | in clock_init()
713 setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK | in clock_init()
/external/u-boot/arch/arm/include/asm/arch-mx8m/
Dclock.h533 #define SSCG_PLL_CLKE_MASK BIT(25) macro