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Searched refs:SSCG_PLL_REF_DIVR1_MASK (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/include/asm/arch-mx8m/
Dclock.h561 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) macro
563 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
/external/u-boot/arch/arm/mach-imx/mx8m/
Dclock.c224 divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >> in decode_sscg_pll()