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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Freescale i.MX28 SSP Register Definitions
4  *
5  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6  *
7  * Based on code from LTIB:
8  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
9  */
10 
11 #ifndef __MX28_REGS_SSP_H__
12 #define __MX28_REGS_SSP_H__
13 
14 #include <asm/mach-imx/regs-common.h>
15 
16 #ifndef	__ASSEMBLY__
17 #if defined(CONFIG_MX23)
18 struct mxs_ssp_regs {
19 	mxs_reg_32(hw_ssp_ctrl0)
20 	mxs_reg_32(hw_ssp_cmd0)
21 	mxs_reg_32(hw_ssp_cmd1)
22 	mxs_reg_32(hw_ssp_compref)
23 	mxs_reg_32(hw_ssp_compmask)
24 	mxs_reg_32(hw_ssp_timing)
25 	mxs_reg_32(hw_ssp_ctrl1)
26 	mxs_reg_32(hw_ssp_data)
27 	mxs_reg_32(hw_ssp_sdresp0)
28 	mxs_reg_32(hw_ssp_sdresp1)
29 	mxs_reg_32(hw_ssp_sdresp2)
30 	mxs_reg_32(hw_ssp_sdresp3)
31 	mxs_reg_32(hw_ssp_status)
32 
33 	uint32_t	reserved1[12];
34 
35 	mxs_reg_32(hw_ssp_debug)
36 	mxs_reg_32(hw_ssp_version)
37 };
38 #elif defined(CONFIG_MX28)
39 struct mxs_ssp_regs {
40 	mxs_reg_32(hw_ssp_ctrl0)
41 	mxs_reg_32(hw_ssp_cmd0)
42 	mxs_reg_32(hw_ssp_cmd1)
43 	mxs_reg_32(hw_ssp_xfer_size)
44 	mxs_reg_32(hw_ssp_block_size)
45 	mxs_reg_32(hw_ssp_compref)
46 	mxs_reg_32(hw_ssp_compmask)
47 	mxs_reg_32(hw_ssp_timing)
48 	mxs_reg_32(hw_ssp_ctrl1)
49 	mxs_reg_32(hw_ssp_data)
50 	mxs_reg_32(hw_ssp_sdresp0)
51 	mxs_reg_32(hw_ssp_sdresp1)
52 	mxs_reg_32(hw_ssp_sdresp2)
53 	mxs_reg_32(hw_ssp_sdresp3)
54 	mxs_reg_32(hw_ssp_ddr_ctrl)
55 	mxs_reg_32(hw_ssp_dll_ctrl)
56 	mxs_reg_32(hw_ssp_status)
57 	mxs_reg_32(hw_ssp_dll_sts)
58 	mxs_reg_32(hw_ssp_debug)
59 	mxs_reg_32(hw_ssp_version)
60 };
61 #endif
62 
mxs_ssp_bus_id_valid(int bus)63 static inline int mxs_ssp_bus_id_valid(int bus)
64 {
65 #if defined(CONFIG_MX23)
66 	const unsigned int mxs_ssp_chan_count = 2;
67 #elif defined(CONFIG_MX28)
68 	const unsigned int mxs_ssp_chan_count = 4;
69 #endif
70 
71 	if (bus >= mxs_ssp_chan_count)
72 		return 0;
73 
74 	if (bus < 0)
75 		return 0;
76 
77 	return 1;
78 }
79 
mxs_ssp_clock_by_bus(unsigned int clock)80 static inline int mxs_ssp_clock_by_bus(unsigned int clock)
81 {
82 #if defined(CONFIG_MX23)
83 	return 0;
84 #elif defined(CONFIG_MX28)
85 	return clock;
86 #endif
87 }
88 
mxs_ssp_regs_by_bus(unsigned int port)89 static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port)
90 {
91 	switch (port) {
92 	case 0:
93 		return (struct mxs_ssp_regs *)MXS_SSP0_BASE;
94 	case 1:
95 		return (struct mxs_ssp_regs *)MXS_SSP1_BASE;
96 #ifdef CONFIG_MX28
97 	case 2:
98 		return (struct mxs_ssp_regs *)MXS_SSP2_BASE;
99 	case 3:
100 		return (struct mxs_ssp_regs *)MXS_SSP3_BASE;
101 #endif
102 	default:
103 		return NULL;
104 	}
105 }
106 #endif
107 
108 #define	SSP_CTRL0_SFTRST			(1 << 31)
109 #define	SSP_CTRL0_CLKGATE			(1 << 30)
110 #define	SSP_CTRL0_RUN				(1 << 29)
111 #define	SSP_CTRL0_SDIO_IRQ_CHECK		(1 << 28)
112 #define	SSP_CTRL0_LOCK_CS			(1 << 27)
113 #define	SSP_CTRL0_IGNORE_CRC			(1 << 26)
114 #define	SSP_CTRL0_READ				(1 << 25)
115 #define	SSP_CTRL0_DATA_XFER			(1 << 24)
116 #define	SSP_CTRL0_BUS_WIDTH_MASK		(0x3 << 22)
117 #define	SSP_CTRL0_BUS_WIDTH_OFFSET		22
118 #define	SSP_CTRL0_BUS_WIDTH_ONE_BIT		(0x0 << 22)
119 #define	SSP_CTRL0_BUS_WIDTH_FOUR_BIT		(0x1 << 22)
120 #define	SSP_CTRL0_BUS_WIDTH_EIGHT_BIT		(0x2 << 22)
121 #define	SSP_CTRL0_WAIT_FOR_IRQ			(1 << 21)
122 #define	SSP_CTRL0_WAIT_FOR_CMD			(1 << 20)
123 #define	SSP_CTRL0_LONG_RESP			(1 << 19)
124 #define	SSP_CTRL0_CHECK_RESP			(1 << 18)
125 #define	SSP_CTRL0_GET_RESP			(1 << 17)
126 #define	SSP_CTRL0_ENABLE			(1 << 16)
127 
128 #ifdef CONFIG_MX23
129 #define	SSP_CTRL0_XFER_COUNT_OFFSET		0
130 #define	SSP_CTRL0_XFER_COUNT_MASK		0xffff
131 #endif
132 
133 #define	SSP_CMD0_SOFT_TERMINATE			(1 << 26)
134 #define	SSP_CMD0_DBL_DATA_RATE_EN		(1 << 25)
135 #define	SSP_CMD0_PRIM_BOOT_OP_EN		(1 << 24)
136 #define	SSP_CMD0_BOOT_ACK_EN			(1 << 23)
137 #define	SSP_CMD0_SLOW_CLKING_EN			(1 << 22)
138 #define	SSP_CMD0_CONT_CLKING_EN			(1 << 21)
139 #define	SSP_CMD0_APPEND_8CYC			(1 << 20)
140 #if defined(CONFIG_MX23)
141 #define	SSP_CMD0_BLOCK_SIZE_MASK		(0xf << 16)
142 #define	SSP_CMD0_BLOCK_SIZE_OFFSET		16
143 #define	SSP_CMD0_BLOCK_COUNT_MASK		(0xff << 8)
144 #define	SSP_CMD0_BLOCK_COUNT_OFFSET		8
145 #endif
146 #define	SSP_CMD0_CMD_MASK			0xff
147 #define	SSP_CMD0_CMD_OFFSET			0
148 #define	SSP_CMD0_CMD_MMC_GO_IDLE_STATE		0x00
149 #define	SSP_CMD0_CMD_MMC_SEND_OP_COND		0x01
150 #define	SSP_CMD0_CMD_MMC_ALL_SEND_CID		0x02
151 #define	SSP_CMD0_CMD_MMC_SET_RELATIVE_ADDR	0x03
152 #define	SSP_CMD0_CMD_MMC_SET_DSR		0x04
153 #define	SSP_CMD0_CMD_MMC_RESERVED_5		0x05
154 #define	SSP_CMD0_CMD_MMC_SWITCH			0x06
155 #define	SSP_CMD0_CMD_MMC_SELECT_DESELECT_CARD	0x07
156 #define	SSP_CMD0_CMD_MMC_SEND_EXT_CSD		0x08
157 #define	SSP_CMD0_CMD_MMC_SEND_CSD		0x09
158 #define	SSP_CMD0_CMD_MMC_SEND_CID		0x0a
159 #define	SSP_CMD0_CMD_MMC_READ_DAT_UNTIL_STOP	0x0b
160 #define	SSP_CMD0_CMD_MMC_STOP_TRANSMISSION	0x0c
161 #define	SSP_CMD0_CMD_MMC_SEND_STATUS		0x0d
162 #define	SSP_CMD0_CMD_MMC_BUSTEST_R		0x0e
163 #define	SSP_CMD0_CMD_MMC_GO_INACTIVE_STATE	0x0f
164 #define	SSP_CMD0_CMD_MMC_SET_BLOCKLEN		0x10
165 #define	SSP_CMD0_CMD_MMC_READ_SINGLE_BLOCK	0x11
166 #define	SSP_CMD0_CMD_MMC_READ_MULTIPLE_BLOCK	0x12
167 #define	SSP_CMD0_CMD_MMC_BUSTEST_W		0x13
168 #define	SSP_CMD0_CMD_MMC_WRITE_DAT_UNTIL_STOP	0x14
169 #define	SSP_CMD0_CMD_MMC_SET_BLOCK_COUNT	0x17
170 #define	SSP_CMD0_CMD_MMC_WRITE_BLOCK		0x18
171 #define	SSP_CMD0_CMD_MMC_WRITE_MULTIPLE_BLOCK	0x19
172 #define	SSP_CMD0_CMD_MMC_PROGRAM_CID		0x1a
173 #define	SSP_CMD0_CMD_MMC_PROGRAM_CSD		0x1b
174 #define	SSP_CMD0_CMD_MMC_SET_WRITE_PROT		0x1c
175 #define	SSP_CMD0_CMD_MMC_CLR_WRITE_PROT		0x1d
176 #define	SSP_CMD0_CMD_MMC_SEND_WRITE_PROT	0x1e
177 #define	SSP_CMD0_CMD_MMC_ERASE_GROUP_START	0x23
178 #define	SSP_CMD0_CMD_MMC_ERASE_GROUP_END	0x24
179 #define	SSP_CMD0_CMD_MMC_ERASE			0x26
180 #define	SSP_CMD0_CMD_MMC_FAST_IO		0x27
181 #define	SSP_CMD0_CMD_MMC_GO_IRQ_STATE		0x28
182 #define	SSP_CMD0_CMD_MMC_LOCK_UNLOCK		0x2a
183 #define	SSP_CMD0_CMD_MMC_APP_CMD		0x37
184 #define	SSP_CMD0_CMD_MMC_GEN_CMD		0x38
185 #define	SSP_CMD0_CMD_SD_GO_IDLE_STATE		0x00
186 #define	SSP_CMD0_CMD_SD_ALL_SEND_CID		0x02
187 #define	SSP_CMD0_CMD_SD_SEND_RELATIVE_ADDR	0x03
188 #define	SSP_CMD0_CMD_SD_SET_DSR			0x04
189 #define	SSP_CMD0_CMD_SD_IO_SEND_OP_COND		0x05
190 #define	SSP_CMD0_CMD_SD_SELECT_DESELECT_CARD	0x07
191 #define	SSP_CMD0_CMD_SD_SEND_CSD		0x09
192 #define	SSP_CMD0_CMD_SD_SEND_CID		0x0a
193 #define	SSP_CMD0_CMD_SD_STOP_TRANSMISSION	0x0c
194 #define	SSP_CMD0_CMD_SD_SEND_STATUS		0x0d
195 #define	SSP_CMD0_CMD_SD_GO_INACTIVE_STATE	0x0f
196 #define	SSP_CMD0_CMD_SD_SET_BLOCKLEN		0x10
197 #define	SSP_CMD0_CMD_SD_READ_SINGLE_BLOCK	0x11
198 #define	SSP_CMD0_CMD_SD_READ_MULTIPLE_BLOCK	0x12
199 #define	SSP_CMD0_CMD_SD_WRITE_BLOCK		0x18
200 #define	SSP_CMD0_CMD_SD_WRITE_MULTIPLE_BLOCK	0x19
201 #define	SSP_CMD0_CMD_SD_PROGRAM_CSD		0x1b
202 #define	SSP_CMD0_CMD_SD_SET_WRITE_PROT		0x1c
203 #define	SSP_CMD0_CMD_SD_CLR_WRITE_PROT		0x1d
204 #define	SSP_CMD0_CMD_SD_SEND_WRITE_PROT		0x1e
205 #define	SSP_CMD0_CMD_SD_ERASE_WR_BLK_START	0x20
206 #define	SSP_CMD0_CMD_SD_ERASE_WR_BLK_END	0x21
207 #define	SSP_CMD0_CMD_SD_ERASE_GROUP_START	0x23
208 #define	SSP_CMD0_CMD_SD_ERASE_GROUP_END		0x24
209 #define	SSP_CMD0_CMD_SD_ERASE			0x26
210 #define	SSP_CMD0_CMD_SD_LOCK_UNLOCK		0x2a
211 #define	SSP_CMD0_CMD_SD_IO_RW_DIRECT		0x34
212 #define	SSP_CMD0_CMD_SD_IO_RW_EXTENDED		0x35
213 #define	SSP_CMD0_CMD_SD_APP_CMD			0x37
214 #define	SSP_CMD0_CMD_SD_GEN_CMD			0x38
215 
216 #define	SSP_CMD1_CMD_ARG_MASK			0xffffffff
217 #define	SSP_CMD1_CMD_ARG_OFFSET			0
218 
219 #if defined(CONFIG_MX28)
220 #define	SSP_XFER_SIZE_XFER_COUNT_MASK		0xffffffff
221 #define	SSP_XFER_SIZE_XFER_COUNT_OFFSET		0
222 
223 #define	SSP_BLOCK_SIZE_BLOCK_COUNT_MASK		(0xffffff << 4)
224 #define	SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET	4
225 #define	SSP_BLOCK_SIZE_BLOCK_SIZE_MASK		0xf
226 #define	SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET	0
227 #endif
228 
229 #define	SSP_COMPREF_REFERENCE_MASK		0xffffffff
230 #define	SSP_COMPREF_REFERENCE_OFFSET		0
231 
232 #define	SSP_COMPMASK_MASK_MASK			0xffffffff
233 #define	SSP_COMPMASK_MASK_OFFSET		0
234 
235 #define	SSP_TIMING_TIMEOUT_MASK			(0xffff << 16)
236 #define	SSP_TIMING_TIMEOUT_OFFSET		16
237 #define	SSP_TIMING_CLOCK_DIVIDE_MASK		(0xff << 8)
238 #define	SSP_TIMING_CLOCK_DIVIDE_OFFSET		8
239 #define	SSP_TIMING_CLOCK_RATE_MASK		0xff
240 #define	SSP_TIMING_CLOCK_RATE_OFFSET		0
241 
242 #define	SSP_CTRL1_SDIO_IRQ			(1 << 31)
243 #define	SSP_CTRL1_SDIO_IRQ_EN			(1 << 30)
244 #define	SSP_CTRL1_RESP_ERR_IRQ			(1 << 29)
245 #define	SSP_CTRL1_RESP_ERR_IRQ_EN		(1 << 28)
246 #define	SSP_CTRL1_RESP_TIMEOUT_IRQ		(1 << 27)
247 #define	SSP_CTRL1_RESP_TIMEOUT_IRQ_EN		(1 << 26)
248 #define	SSP_CTRL1_DATA_TIMEOUT_IRQ		(1 << 25)
249 #define	SSP_CTRL1_DATA_TIMEOUT_IRQ_EN		(1 << 24)
250 #define	SSP_CTRL1_DATA_CRC_IRQ			(1 << 23)
251 #define	SSP_CTRL1_DATA_CRC_IRQ_EN		(1 << 22)
252 #define	SSP_CTRL1_FIFO_UNDERRUN_IRQ		(1 << 21)
253 #define	SSP_CTRL1_FIFO_UNDERRUN_EN		(1 << 20)
254 #define	SSP_CTRL1_CEATA_CCS_ERR_IRQ		(1 << 19)
255 #define	SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN		(1 << 18)
256 #define	SSP_CTRL1_RECV_TIMEOUT_IRQ		(1 << 17)
257 #define	SSP_CTRL1_RECV_TIMEOUT_IRQ_EN		(1 << 16)
258 #define	SSP_CTRL1_FIFO_OVERRUN_IRQ		(1 << 15)
259 #define	SSP_CTRL1_FIFO_OVERRUN_IRQ_EN		(1 << 14)
260 #define	SSP_CTRL1_DMA_ENABLE			(1 << 13)
261 #define	SSP_CTRL1_CEATA_CCS_ERR_EN		(1 << 12)
262 #define	SSP_CTRL1_SLAVE_OUT_DISABLE		(1 << 11)
263 #define	SSP_CTRL1_PHASE				(1 << 10)
264 #define	SSP_CTRL1_POLARITY			(1 << 9)
265 #define	SSP_CTRL1_SLAVE_MODE			(1 << 8)
266 #define	SSP_CTRL1_WORD_LENGTH_MASK		(0xf << 4)
267 #define	SSP_CTRL1_WORD_LENGTH_OFFSET		4
268 #define	SSP_CTRL1_WORD_LENGTH_RESERVED0		(0x0 << 4)
269 #define	SSP_CTRL1_WORD_LENGTH_RESERVED1		(0x1 << 4)
270 #define	SSP_CTRL1_WORD_LENGTH_RESERVED2		(0x2 << 4)
271 #define	SSP_CTRL1_WORD_LENGTH_FOUR_BITS		(0x3 << 4)
272 #define	SSP_CTRL1_WORD_LENGTH_EIGHT_BITS	(0x7 << 4)
273 #define	SSP_CTRL1_WORD_LENGTH_SIXTEEN_BITS	(0xf << 4)
274 #define	SSP_CTRL1_SSP_MODE_MASK			0xf
275 #define	SSP_CTRL1_SSP_MODE_OFFSET		0
276 #define	SSP_CTRL1_SSP_MODE_SPI			0x0
277 #define	SSP_CTRL1_SSP_MODE_SSI			0x1
278 #define	SSP_CTRL1_SSP_MODE_SD_MMC		0x3
279 #define	SSP_CTRL1_SSP_MODE_MS			0x4
280 
281 #define	SSP_DATA_DATA_MASK			0xffffffff
282 #define	SSP_DATA_DATA_OFFSET			0
283 
284 #define	SSP_SDRESP0_RESP0_MASK			0xffffffff
285 #define	SSP_SDRESP0_RESP0_OFFSET		0
286 
287 #define	SSP_SDRESP1_RESP1_MASK			0xffffffff
288 #define	SSP_SDRESP1_RESP1_OFFSET		0
289 
290 #define	SSP_SDRESP2_RESP2_MASK			0xffffffff
291 #define	SSP_SDRESP2_RESP2_OFFSET		0
292 
293 #define	SSP_SDRESP3_RESP3_MASK			0xffffffff
294 #define	SSP_SDRESP3_RESP3_OFFSET		0
295 
296 #define	SSP_DDR_CTRL_DMA_BURST_TYPE_MASK	(0x3 << 30)
297 #define	SSP_DDR_CTRL_DMA_BURST_TYPE_OFFSET	30
298 #define	SSP_DDR_CTRL_NIBBLE_POS			(1 << 1)
299 #define	SSP_DDR_CTRL_TXCLK_DELAY_TYPE		(1 << 0)
300 
301 #define	SSP_DLL_CTRL_REF_UPDATE_INT_MASK	(0xf << 28)
302 #define	SSP_DLL_CTRL_REF_UPDATE_INT_OFFSET	28
303 #define	SSP_DLL_CTRL_SLV_UPDATE_INT_MASK	(0xff << 20)
304 #define	SSP_DLL_CTRL_SLV_UPDATE_INT_OFFSET	20
305 #define	SSP_DLL_CTRL_SLV_OVERRIDE_VAL_MASK	(0x3f << 10)
306 #define	SSP_DLL_CTRL_SLV_OVERRIDE_VAL_OFFSET	10
307 #define	SSP_DLL_CTRL_SLV_OVERRIDE		(1 << 9)
308 #define	SSP_DLL_CTRL_GATE_UPDATE		(1 << 7)
309 #define	SSP_DLL_CTRL_SLV_DLY_TARGET_MASK	(0xf << 3)
310 #define	SSP_DLL_CTRL_SLV_DLY_TARGET_OFFSET	3
311 #define	SSP_DLL_CTRL_SLV_FORCE_UPD		(1 << 2)
312 #define	SSP_DLL_CTRL_RESET			(1 << 1)
313 #define	SSP_DLL_CTRL_ENABLE			(1 << 0)
314 
315 #define	SSP_STATUS_PRESENT			(1 << 31)
316 #define	SSP_STATUS_MS_PRESENT			(1 << 30)
317 #define	SSP_STATUS_SD_PRESENT			(1 << 29)
318 #define	SSP_STATUS_CARD_DETECT			(1 << 28)
319 #define	SSP_STATUS_DMABURST			(1 << 22)
320 #define	SSP_STATUS_DMASENSE			(1 << 21)
321 #define	SSP_STATUS_DMATERM			(1 << 20)
322 #define	SSP_STATUS_DMAREQ			(1 << 19)
323 #define	SSP_STATUS_DMAEND			(1 << 18)
324 #define	SSP_STATUS_SDIO_IRQ			(1 << 17)
325 #define	SSP_STATUS_RESP_CRC_ERR			(1 << 16)
326 #define	SSP_STATUS_RESP_ERR			(1 << 15)
327 #define	SSP_STATUS_RESP_TIMEOUT			(1 << 14)
328 #define	SSP_STATUS_DATA_CRC_ERR			(1 << 13)
329 #define	SSP_STATUS_TIMEOUT			(1 << 12)
330 #define	SSP_STATUS_RECV_TIMEOUT_STAT		(1 << 11)
331 #define	SSP_STATUS_CEATA_CCS_ERR		(1 << 10)
332 #define	SSP_STATUS_FIFO_OVRFLW			(1 << 9)
333 #define	SSP_STATUS_FIFO_FULL			(1 << 8)
334 #define	SSP_STATUS_FIFO_EMPTY			(1 << 5)
335 #define	SSP_STATUS_FIFO_UNDRFLW			(1 << 4)
336 #define	SSP_STATUS_CMD_BUSY			(1 << 3)
337 #define	SSP_STATUS_DATA_BUSY			(1 << 2)
338 #define	SSP_STATUS_BUSY				(1 << 0)
339 
340 #define	SSP_DLL_STS_REF_SEL_MASK		(0x3f << 8)
341 #define	SSP_DLL_STS_REF_SEL_OFFSET		8
342 #define	SSP_DLL_STS_SLV_SEL_MASK		(0x3f << 2)
343 #define	SSP_DLL_STS_SLV_SEL_OFFSET		2
344 #define	SSP_DLL_STS_REF_LOCK			(1 << 1)
345 #define	SSP_DLL_STS_SLV_LOCK			(1 << 0)
346 
347 #define	SSP_DEBUG_DATACRC_ERR_MASK		(0xf << 28)
348 #define	SSP_DEBUG_DATACRC_ERR_OFFSET		28
349 #define	SSP_DEBUG_DATA_STALL			(1 << 27)
350 #define	SSP_DEBUG_DAT_SM_MASK			(0x7 << 24)
351 #define	SSP_DEBUG_DAT_SM_OFFSET			24
352 #define	SSP_DEBUG_DAT_SM_DSM_IDLE		(0x0 << 24)
353 #define	SSP_DEBUG_DAT_SM_DSM_WORD		(0x2 << 24)
354 #define	SSP_DEBUG_DAT_SM_DSM_CRC1		(0x3 << 24)
355 #define	SSP_DEBUG_DAT_SM_DSM_CRC2		(0x4 << 24)
356 #define	SSP_DEBUG_DAT_SM_DSM_END		(0x5 << 24)
357 #define	SSP_DEBUG_MSTK_SM_MASK			(0xf << 20)
358 #define	SSP_DEBUG_MSTK_SM_OFFSET		20
359 #define	SSP_DEBUG_MSTK_SM_MSTK_IDLE		(0x0 << 20)
360 #define	SSP_DEBUG_MSTK_SM_MSTK_CKON		(0x1 << 20)
361 #define	SSP_DEBUG_MSTK_SM_MSTK_BS1		(0x2 << 20)
362 #define	SSP_DEBUG_MSTK_SM_MSTK_TPC		(0x3 << 20)
363 #define	SSP_DEBUG_MSTK_SM_MSTK_BS2		(0x4 << 20)
364 #define	SSP_DEBUG_MSTK_SM_MSTK_HDSHK		(0x5 << 20)
365 #define	SSP_DEBUG_MSTK_SM_MSTK_BS3		(0x6 << 20)
366 #define	SSP_DEBUG_MSTK_SM_MSTK_RW		(0x7 << 20)
367 #define	SSP_DEBUG_MSTK_SM_MSTK_CRC1		(0x8 << 20)
368 #define	SSP_DEBUG_MSTK_SM_MSTK_CRC2		(0x9 << 20)
369 #define	SSP_DEBUG_MSTK_SM_MSTK_BS0		(0xa << 20)
370 #define	SSP_DEBUG_MSTK_SM_MSTK_END1		(0xb << 20)
371 #define	SSP_DEBUG_MSTK_SM_MSTK_END2W		(0xc << 20)
372 #define	SSP_DEBUG_MSTK_SM_MSTK_END2R		(0xd << 20)
373 #define	SSP_DEBUG_MSTK_SM_MSTK_DONE		(0xe << 20)
374 #define	SSP_DEBUG_CMD_OE			(1 << 19)
375 #define	SSP_DEBUG_DMA_SM_MASK			(0x7 << 16)
376 #define	SSP_DEBUG_DMA_SM_OFFSET			16
377 #define	SSP_DEBUG_DMA_SM_DMA_IDLE		(0x0 << 16)
378 #define	SSP_DEBUG_DMA_SM_DMA_DMAREQ		(0x1 << 16)
379 #define	SSP_DEBUG_DMA_SM_DMA_DMAACK		(0x2 << 16)
380 #define	SSP_DEBUG_DMA_SM_DMA_STALL		(0x3 << 16)
381 #define	SSP_DEBUG_DMA_SM_DMA_BUSY		(0x4 << 16)
382 #define	SSP_DEBUG_DMA_SM_DMA_DONE		(0x5 << 16)
383 #define	SSP_DEBUG_DMA_SM_DMA_COUNT		(0x6 << 16)
384 #define	SSP_DEBUG_MMC_SM_MASK			(0xf << 12)
385 #define	SSP_DEBUG_MMC_SM_OFFSET			12
386 #define	SSP_DEBUG_MMC_SM_MMC_IDLE		(0x0 << 12)
387 #define	SSP_DEBUG_MMC_SM_MMC_CMD		(0x1 << 12)
388 #define	SSP_DEBUG_MMC_SM_MMC_TRC		(0x2 << 12)
389 #define	SSP_DEBUG_MMC_SM_MMC_RESP		(0x3 << 12)
390 #define	SSP_DEBUG_MMC_SM_MMC_RPRX		(0x4 << 12)
391 #define	SSP_DEBUG_MMC_SM_MMC_TX			(0x5 << 12)
392 #define	SSP_DEBUG_MMC_SM_MMC_CTOK		(0x6 << 12)
393 #define	SSP_DEBUG_MMC_SM_MMC_RX			(0x7 << 12)
394 #define	SSP_DEBUG_MMC_SM_MMC_CCS		(0x8 << 12)
395 #define	SSP_DEBUG_MMC_SM_MMC_PUP		(0x9 << 12)
396 #define	SSP_DEBUG_MMC_SM_MMC_WAIT		(0xa << 12)
397 #define	SSP_DEBUG_CMD_SM_MASK			(0x3 << 10)
398 #define	SSP_DEBUG_CMD_SM_OFFSET			10
399 #define	SSP_DEBUG_CMD_SM_CSM_IDLE		(0x0 << 10)
400 #define	SSP_DEBUG_CMD_SM_CSM_INDEX		(0x1 << 10)
401 #define	SSP_DEBUG_CMD_SM_CSM_ARG		(0x2 << 10)
402 #define	SSP_DEBUG_CMD_SM_CSM_CRC		(0x3 << 10)
403 #define	SSP_DEBUG_SSP_CMD			(1 << 9)
404 #define	SSP_DEBUG_SSP_RESP			(1 << 8)
405 #define	SSP_DEBUG_SSP_RXD_MASK			0xff
406 #define	SSP_DEBUG_SSP_RXD_OFFSET		0
407 
408 #define	SSP_VERSION_MAJOR_MASK			(0xff << 24)
409 #define	SSP_VERSION_MAJOR_OFFSET		24
410 #define	SSP_VERSION_MINOR_MASK			(0xff << 16)
411 #define	SSP_VERSION_MINOR_OFFSET		16
412 #define	SSP_VERSION_STEP_MASK			0xffff
413 #define	SSP_VERSION_STEP_OFFSET			0
414 
415 #endif /* __MX28_REGS_SSP_H__ */
416