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Searched refs:STLLRB (Results 1 – 16 of 16) sorted by relevance

/external/vixl/src/aarch64/
Dcpu-features-auditor-aarch64.cc504 case STLLRB: in VisitLoadStoreExclusive()
Dconstants-aarch64.h1017 STLLRB = LoadStoreExclusiveFixed | 0x00800000, enumerator
Ddisasm-aarch64.cc1368 V(STLLRB, "stllrb", "'Wt") \
Dsimulator-aarch64.cc1924 case STLLRB: in VisitLoadStoreExclusive()
Dassembler-aarch64.cc1530 Emit(STLLRB | Rs_mask | Rt(rt) | Rt2_mask | RnSP(dst.GetBaseRegister())); in stllrb()
/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp1114 case AArch64::STLLRB: in DecodeExclusiveLdStInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp1312 case AArch64::STLLRB: in DecodeExclusiveLdStInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SchedThunderX2T99.td1877 (instrs STLLRB, STLLRH, STLLRW, STLLRX)>;
DAArch64InstrInfo.td2766 def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">;
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenMCCodeEmitter.inc3696 UINT64_C(144669696), // STLLRB
9858 case AArch64::STLLRB:
15748 Feature_HasV8_1a | 0, // STLLRB = 3683
DAArch64GenAsmWriter.inc4495 2253964715U, // STLLRB
9014 27U, // STLLRB
DAArch64GenAsmWriter1.inc5444 205622185U, // STLLRB
9963 27U, // STLLRB
DAArch64GenInstrInfo.inc3698 STLLRB = 3683,
9585 …deledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #3683 = STLLRB
DAArch64GenAsmMatcher.inc17378 …{ 4674 /* stllrb */, AArch64::STLLRB, Convert__Reg1_0__GPR64sp01_2, Feature_HasV8_1a, { MCK_GPR32,…
23847 …{ 4674 /* stllrb */, AArch64::STLLRB, Convert__Reg1_0__GPR64sp01_2, Feature_HasV8_1a, { MCK_GPR32,…
DAArch64GenDisassemblerTables.inc6148 /* 28828 */ MCD::OPC_Decode, 227, 28, 145, 1, // Opcode: STLLRB
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td2485 def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">;