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/external/llvm/lib/Target/Hexagon/
DHexagonMachineScheduler.cpp43 bool VLIWResourceModel::isResourceAvailable(SUnit *SU) { in isResourceAvailable() argument
44 if (!SU || !SU->getInstr()) in isResourceAvailable()
49 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
51 if (!ResourcesModel->canReserveResources(*SU->getInstr())) in isResourceAvailable()
75 if (I->getSUnit() == SU) in isResourceAvailable()
83 bool VLIWResourceModel::reserveResources(SUnit *SU) { in reserveResources() argument
86 if (!SU) { in reserveResources()
94 if (!isResourceAvailable(SU)) { in reserveResources()
101 switch (SU->getInstr()->getOpcode()) { in reserveResources()
103 ResourcesModel->reserveResources(*SU->getInstr()); in reserveResources()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonMachineScheduler.cpp98 bool VLIWResourceModel::isResourceAvailable(SUnit *SU, bool IsTop) { in isResourceAvailable() argument
99 if (!SU || !SU->getInstr()) in isResourceAvailable()
104 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
106 if (!ResourcesModel->canReserveResources(*SU->getInstr())) in isResourceAvailable()
119 MachineBasicBlock *MBB = SU->getInstr()->getParent(); in isResourceAvailable()
127 if (hasDependence(Packet[i], SU, QII)) in isResourceAvailable()
131 if (hasDependence(SU, Packet[i], QII)) in isResourceAvailable()
138 bool VLIWResourceModel::reserveResources(SUnit *SU, bool IsTop) { in reserveResources() argument
141 if (!SU) { in reserveResources()
149 if (!isResourceAvailable(SU, IsTop) || in reserveResources()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp68 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { in numberRCValPredInSU() argument
70 for (SDep &Pred : SU->Preds) { in numberRCValPredInSU()
104 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU, in numberRCValSuccInSU() argument
107 for (const SDep &Succ : SU->Succs) { in numberRCValSuccInSU()
141 static unsigned numberCtrlDepsInSU(SUnit *SU) { in numberCtrlDepsInSU() argument
143 for (const SDep &Succ : SU->Succs) in numberCtrlDepsInSU()
150 static unsigned numberCtrlPredInSU(SUnit *SU) { in numberCtrlPredInSU() argument
152 for (SDep &Pred : SU->Preds) in numberCtrlPredInSU()
167 SUnit *SU = &(*SUnits)[i]; in initNodes() local
168 initNumRegDefsLeft(SU); in initNodes()
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DScheduleDAGRRList.cpp213 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { in IsReachable() argument
214 return Topo.IsReachable(SU, TargetSU); in IsReachable()
219 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { in WillCreateCycle() argument
220 return Topo.WillCreateCycle(SU, TargetSU); in WillCreateCycle()
226 void AddPred(SUnit *SU, const SDep &D) { in AddPred() argument
227 Topo.AddPred(SU, D.getSUnit()); in AddPred()
228 SU->addPred(D); in AddPred()
234 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred() argument
235 Topo.RemovePred(SU, D.getSUnit()); in RemovePred()
236 SU->removePred(D); in RemovePred()
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/external/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp70 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { in numberRCValPredInSU() argument
72 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in numberRCValPredInSU()
107 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU, in numberRCValSuccInSU() argument
110 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in numberRCValSuccInSU()
145 static unsigned numberCtrlDepsInSU(SUnit *SU) { in numberCtrlDepsInSU() argument
147 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in numberCtrlDepsInSU()
155 static unsigned numberCtrlPredInSU(SUnit *SU) { in numberCtrlPredInSU() argument
157 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in numberCtrlPredInSU()
173 SUnit *SU = &(*SUnits)[i]; in initNodes() local
174 initNumRegDefsLeft(SU); in initNodes()
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DScheduleDAGRRList.cpp186 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { in IsReachable() argument
187 return Topo.IsReachable(SU, TargetSU); in IsReachable()
192 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { in WillCreateCycle() argument
193 return Topo.WillCreateCycle(SU, TargetSU); in WillCreateCycle()
199 void AddPred(SUnit *SU, const SDep &D) { in AddPred() argument
200 Topo.AddPred(SU, D.getSUnit()); in AddPred()
201 SU->addPred(D); in AddPred()
207 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred() argument
208 Topo.RemovePred(SU, D.getSUnit()); in RemovePred()
209 SU->removePred(D); in RemovePred()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DGCNMinRegStrategy.cpp32 const SUnit *SU; member
36 : SU(SU_), Priority(Priority_) {} in Candidate()
45 bool isScheduled(const SUnit *SU) const { in isScheduled()
46 assert(!SU->isBoundaryNode()); in isScheduled()
47 return NumPreds[SU->NodeNum] == std::numeric_limits<unsigned>::max(); in isScheduled()
50 void setIsScheduled(const SUnit *SU) { in setIsScheduled() argument
51 assert(!SU->isBoundaryNode()); in setIsScheduled()
52 NumPreds[SU->NodeNum] = std::numeric_limits<unsigned>::max(); in setIsScheduled()
55 unsigned getNumPreds(const SUnit *SU) const { in getNumPreds()
56 assert(!SU->isBoundaryNode()); in getNumPreds()
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DGCNILPSched.cpp24 SUnit *SU; member
27 : SU(SU_) {} in Candidate()
41 unsigned getNodePriority(const SUnit *SU) const;
48 void releasePredecessors(const SUnit* SU);
59 CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) { in CalcNodeSethiUllmanNumber() argument
60 unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum]; in CalcNodeSethiUllmanNumber()
65 for (const SDep &Pred : SU->Preds) { in CalcNodeSethiUllmanNumber()
87 unsigned GCNILPScheduler::getNodePriority(const SUnit *SU) const { in getNodePriority()
88 assert(SU->NodeNum < SUNumbers.size()); in getNodePriority()
89 if (SU->NumSuccs == 0 && SU->NumPreds != 0) in getNodePriority()
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DSIMachineScheduler.cpp198 void SIScheduleBlock::addUnit(SUnit *SU) { in addUnit() argument
199 NodeNum2Index[SU->NodeNum] = SUnits.size(); in addUnit()
200 SUnits.push_back(SU); in addUnit()
206 dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason); in traceCandidate()
258 if (TryCand.SU->NodeNum < Cand.SU->NodeNum) { in tryCandidateTopDown()
266 for (SUnit* SU : TopReadySUs) { in pickNode()
271 TryCand.SU = SU; in pickNode()
272 TopRPTracker.getDownwardPressure(SU->getInstr(), pressure, MaxPressure); in pickNode()
275 TryCand.IsLowLatency = DAG->IsLowLatencySU[SU->NodeNum]; in pickNode()
276 TryCand.LowLatencyOffset = DAG->LowLatencyOffset[SU->NodeNum]; in pickNode()
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DR600MachineScheduler.cpp59 SUnit *SU = nullptr; in pickNode() local
99 if (!SU && ((AllowSwitchToAlu && CurInstKind != IDAlu) || in pickNode()
102 SU = pickAlu(); in pickNode()
103 if (!SU && !PhysicalRegCopy.empty()) { in pickNode()
104 SU = PhysicalRegCopy.front(); in pickNode()
107 if (SU) { in pickNode()
114 if (!SU) { in pickNode()
116 SU = pickOther(IDFetch); in pickNode()
117 if (SU) in pickNode()
122 if (!SU) { in pickNode()
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Daarch64-stp-cluster.ll6 ; CHECK:Cluster ld/st SU(4) - SU(3)
7 ; CHECK:Cluster ld/st SU(2) - SU(5)
8 ; CHECK:SU(4): STRXui %1:gpr64, %0:gpr64common, 1
9 ; CHECK:SU(3): STRXui %1:gpr64, %0:gpr64common, 2
10 ; CHECK:SU(2): STRXui %1:gpr64, %0:gpr64common, 3
11 ; CHECK:SU(5): STRXui %1:gpr64, %0:gpr64common, 4
27 ; CHECK:Cluster ld/st SU(4) - SU(3)
28 ; CHECK:Cluster ld/st SU(2) - SU(5)
29 ; CHECK:SU(4): STRWui %1:gpr32, %0:gpr64common, 1
30 ; CHECK:SU(3): STRWui %1:gpr32, %0:gpr64common, 2
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Darm64-ldp-cluster.ll9 ; CHECK: Cluster ld/st SU(1) - SU(2)
10 ; CHECK: SU(1): %{{[0-9]+}}:gpr32 = LDRWui
11 ; CHECK: SU(2): %{{[0-9]+}}:gpr32 = LDRWui
14 ; EXYNOSM1: Cluster ld/st SU(1) - SU(2)
15 ; EXYNOSM1: SU(1): %{{[0-9]+}}:gpr32 = LDRWui
16 ; EXYNOSM1: SU(2): %{{[0-9]+}}:gpr32 = LDRWui
29 ; CHECK: Cluster ld/st SU(1) - SU(2)
30 ; CHECK: SU(1): %{{[0-9]+}}:gpr64 = LDRSWui
31 ; CHECK: SU(2): %{{[0-9]+}}:gpr64 = LDRSWui
34 ; EXYNOSM1: Cluster ld/st SU(1) - SU(2)
[all …]
/external/llvm/test/CodeGen/AArch64/
Daarch64-stp-cluster.ll6 ; CHECK:Cluster ld/st SU(4) - SU(3)
7 ; CHECK:Cluster ld/st SU(2) - SU(5)
8 ; CHECK:SU(4): STRXui %vreg1, %vreg0, 1
9 ; CHECK:SU(3): STRXui %vreg1, %vreg0, 2
10 ; CHECK:SU(2): STRXui %vreg1, %vreg0, 3
11 ; CHECK:SU(5): STRXui %vreg1, %vreg0, 4
27 ; CHECK:Cluster ld/st SU(4) - SU(3)
28 ; CHECK:Cluster ld/st SU(2) - SU(5)
29 ; CHECK:SU(4): STRWui %vreg1, %vreg0, 1
30 ; CHECK:SU(3): STRWui %vreg1, %vreg0, 2
[all …]
Darm64-ldp-cluster.ll8 ; CHECK: Cluster ld/st SU(1) - SU(2)
9 ; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDRWui
10 ; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDRWui
13 ; EXYNOS: Cluster ld/st SU(1) - SU(2)
14 ; EXYNOS: SU(1): %vreg{{[0-9]+}}<def> = LDRWui
15 ; EXYNOS: SU(2): %vreg{{[0-9]+}}<def> = LDRWui
28 ; CHECK: Cluster ld/st SU(1) - SU(2)
29 ; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDRSWui
30 ; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDRSWui
33 ; EXYNOS: Cluster ld/st SU(1) - SU(2)
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DScheduleDAGRRList.cpp190 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { in IsReachable() argument
191 return Topo.IsReachable(SU, TargetSU); in IsReachable()
196 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { in WillCreateCycle() argument
197 return Topo.WillCreateCycle(SU, TargetSU); in WillCreateCycle()
203 void AddPred(SUnit *SU, const SDep &D) { in AddPred() argument
204 Topo.AddPred(SU, D.getSUnit()); in AddPred()
205 SU->addPred(D); in AddPred()
211 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred() argument
212 Topo.RemovePred(SU, D.getSUnit()); in RemovePred()
213 SU->removePred(D); in RemovePred()
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DScheduleDAGFast.cpp82 void AddPred(SUnit *SU, const SDep &D) { in AddPred() argument
83 SU->addPred(D); in AddPred()
88 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred() argument
89 SU->removePred(D); in RemovePred()
93 void ReleasePred(SUnit *SU, SDep *PredEdge);
94 void ReleasePredecessors(SUnit *SU, unsigned CurCycle);
134 void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) { in ReleasePred() argument
155 void ScheduleDAGFast::ReleasePredecessors(SUnit *SU, unsigned CurCycle) { in ReleasePredecessors() argument
157 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in ReleasePredecessors()
159 ReleasePred(SU, &*I); in ReleasePredecessors()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DMachineScheduler.cpp588 for (const SUnit *SU : Queue) in dump() local
589 dbgs() << SU->NodeNum << " "; in dump()
624 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) { in releaseSucc() argument
643 if (SuccSU->TopReadyCycle < SU->TopReadyCycle + SuccEdge->getLatency()) in releaseSucc()
644 SuccSU->TopReadyCycle = SU->TopReadyCycle + SuccEdge->getLatency(); in releaseSucc()
652 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) { in releaseSuccessors() argument
653 for (SDep &Succ : SU->Succs) in releaseSuccessors()
654 releaseSucc(SU, &Succ); in releaseSuccessors()
661 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) { in releasePred() argument
680 if (PredSU->BotReadyCycle < SU->BotReadyCycle + PredEdge->getLatency()) in releasePred()
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DScheduleDAGInstrs.cpp230 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { in addPhysRegDataDeps() argument
231 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); in addPhysRegDataDeps()
242 SUnit *UseSU = I->SU; in addPhysRegDataDeps()
243 if (UseSU == SU) in addPhysRegDataDeps()
252 Dep = SDep(SU, SDep::Artificial); in addPhysRegDataDeps()
256 SU->hasPhysRegDefs = true; in addPhysRegDataDeps()
257 Dep = SDep(SU, SDep::Data, *Alias); in addPhysRegDataDeps()
261 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse, in addPhysRegDataDeps()
264 ST.adjustSchedDependency(SU, UseSU, Dep); in addPhysRegDataDeps()
273 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) { in addPhysRegDeps() argument
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZHazardRecognizer.cpp47 getNumDecoderSlots(SUnit *SU) const { in getNumDecoderSlots()
48 const MCSchedClassDesc *SC = getSchedClass(SU); in getNumDecoderSlots()
62 unsigned SystemZHazardRecognizer::getCurrCycleIdx(SUnit *SU) const { in getCurrCycleIdx()
67 if (SU != nullptr && !fitsIntoCurrentGroup(SU)) { in getCurrCycleIdx()
93 SystemZHazardRecognizer::fitsIntoCurrentGroup(SUnit *SU) const { in fitsIntoCurrentGroup()
94 const MCSchedClassDesc *SC = getSchedClass(SU); in fitsIntoCurrentGroup()
106 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in fitsIntoCurrentGroup()
112 assert ((getNumDecoderSlots(SU) <= 1) && (CurrGroupSize < 3) && in fitsIntoCurrentGroup()
163 void SystemZHazardRecognizer::dumpSU(SUnit *SU, raw_ostream &OS) const { in dumpSU() argument
164 OS << "SU(" << SU->NodeNum << "):"; in dumpSU()
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DSystemZMachineScheduler.cpp29 for (auto &SU : *this) { in dump()
30 HazardRec.dumpSU(SU, dbgs()); in dump()
31 if (SU != *rbegin()) in dump()
176 for (auto *SU : Available) { in pickNode() local
179 Candidate c(SU, *HazardRec); in pickNode()
182 if (Best.SU == nullptr || c < Best) { in pickNode()
187 LLVM_DEBUG(HazardRec->dumpSU(c.SU, dbgs()); c.dumpCosts(); in pickNode()
188 dbgs() << " Height:" << c.SU->getHeight(); dbgs() << "\n";); in pickNode()
192 if (!SU->isScheduleHigh && Best.noCost()) in pickNode()
196 assert (Best.SU != nullptr); in pickNode()
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/external/llvm/lib/CodeGen/
DMachineScheduler.cpp554 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) { in releaseSucc() argument
573 if (SuccSU->TopReadyCycle < SU->TopReadyCycle + SuccEdge->getLatency()) in releaseSucc()
574 SuccSU->TopReadyCycle = SU->TopReadyCycle + SuccEdge->getLatency(); in releaseSucc()
582 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) { in releaseSuccessors() argument
583 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in releaseSuccessors()
585 releaseSucc(SU, &*I); in releaseSuccessors()
593 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) { in releasePred() argument
612 if (PredSU->BotReadyCycle < SU->BotReadyCycle + PredEdge->getLatency()) in releasePred()
613 PredSU->BotReadyCycle = SU->BotReadyCycle + PredEdge->getLatency(); in releasePred()
621 void ScheduleDAGMI::releasePredecessors(SUnit *SU) { in releasePredecessors() argument
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DScheduleDAGInstrs.cpp283 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { in addPhysRegDataDeps() argument
284 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); in addPhysRegDataDeps()
295 SUnit *UseSU = I->SU; in addPhysRegDataDeps()
296 if (UseSU == SU) in addPhysRegDataDeps()
305 Dep = SDep(SU, SDep::Artificial); in addPhysRegDataDeps()
309 SU->hasPhysRegDefs = true; in addPhysRegDataDeps()
310 Dep = SDep(SU, SDep::Data, *Alias); in addPhysRegDataDeps()
314 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse, in addPhysRegDataDeps()
317 ST.adjustSchedDependency(SU, UseSU, Dep); in addPhysRegDataDeps()
326 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) { in addPhysRegDeps() argument
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/external/llvm/lib/Target/AMDGPU/
DSIMachineScheduler.cpp178 void SIScheduleBlock::addUnit(SUnit *SU) { in addUnit() argument
179 NodeNum2Index[SU->NodeNum] = SUnits.size(); in addUnit()
180 SUnits.push_back(SU); in addUnit()
187 dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason); in traceCandidate()
237 if (TryCand.SU->NodeNum < Cand.SU->NodeNum) { in tryCandidateTopDown()
245 for (SUnit* SU : TopReadySUs) { in pickNode()
250 TryCand.SU = SU; in pickNode()
251 TopRPTracker.getDownwardPressure(SU->getInstr(), pressure, MaxPressure); in pickNode()
254 TryCand.IsLowLatency = DAG->IsLowLatencySU[SU->NodeNum]; in pickNode()
255 TryCand.LowLatencyOffset = DAG->LowLatencyOffset[SU->NodeNum]; in pickNode()
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DR600MachineScheduler.cpp58 SUnit *SU = nullptr; in pickNode() local
98 if (!SU && ((AllowSwitchToAlu && CurInstKind != IDAlu) || in pickNode()
101 SU = pickAlu(); in pickNode()
102 if (!SU && !PhysicalRegCopy.empty()) { in pickNode()
103 SU = PhysicalRegCopy.front(); in pickNode()
106 if (SU) { in pickNode()
113 if (!SU) { in pickNode()
115 SU = pickOther(IDFetch); in pickNode()
116 if (SU) in pickNode()
121 if (!SU) { in pickNode()
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DScheduleDAGInstrs.cpp245 SUnit *SU = NewSUnit(MI); in BuildSchedGraph() local
246 SU->isCall = MCID.isCall(); in BuildSchedGraph()
247 SU->isCommutable = MCID.isCommutable(); in BuildSchedGraph()
251 SU->Latency = 1; in BuildSchedGraph()
253 ComputeLatency(SU); in BuildSchedGraph()
279 if (DefSU != SU && in BuildSchedGraph()
282 DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/Reg)); in BuildSchedGraph()
290 if (DefSU != SU && in BuildSchedGraph()
293 DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/ *Alias)); in BuildSchedGraph()
299 unsigned DataLatency = SU->Latency; in BuildSchedGraph()
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