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Searched refs:SUB1 (Results 1 – 12 of 12) sorted by relevance

/external/llvm/lib/Fuzzer/test/
Dfuzzer-dirs.test1 RUN: rm -rf %t/SUB1
2 RUN: mkdir -p %t/SUB1/SUB2/SUB3
3 RUN: echo a > %t/SUB1/a
4 RUN: echo b > %t/SUB1/SUB2/b
5 RUN: echo c > %t/SUB1/SUB2/SUB3/c
6 RUN: LLVMFuzzer-SimpleTest %t/SUB1 -runs=0 2>&1 | FileCheck %s --check-prefix=SUBDIRS
8 RUN: rm -rf %t/SUB1
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/IRCE/
Dranges_of_different_types.ll26 ; CHECK-NEXT: [[SUB1:%[^ ]+]] = sub i32 12, %len
27 ; CHECK-NEXT: [[CMP1:%[^ ]+]] = icmp sgt i32 [[SUB1]], -102
28 ; CHECK-NEXT: [[SMAX:%[^ ]+]] = select i1 [[CMP1]], i32 [[SUB1]], i32 -102
87 ; CHECK-NEXT: [[SUB1:%[^ ]+]] = sub i32 [[ADD1]], %len
88 ; CHECK-NEXT: [[CMP2:%[^ ]+]] = icmp sgt i32 [[SUB1]], -102
89 ; CHECK-NEXT: [[SMAX2:%[^ ]+]] = select i1 [[CMP2]], i32 [[SUB1]], i32 -102
154 ; CHECK-NEXT: [[SUB1:%[^ ]+]] = sub i32 -2, %len
158 ; CHECK-NEXT: [[SUB3:%[^ ]+]] = sub i32 [[SUB1]], [[SMAX1]]
211 ; CHECK-NEXT: [[SUB1:%[^ ]+]] = sub i32 -14, %len
212 ; CHECK-NEXT: [[CMP1:%[^ ]+]] = icmp ugt i32 [[SUB1]], -102
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/Reassociate/
Dcanonicalize-neg-const.ll56 ; CHECK-NEXT: [[SUB1:%.*]] = fadd double %x, [[MUL]]
57 ; CHECK-NEXT: ret double [[SUB1]]
104 ; CHECK-NEXT: [[SUB1:%.*]] = fadd double %x, [[DIV]]
105 ; CHECK-NEXT: ret double [[SUB1]]
175 ; CHECK-NEXT: [[SUB1:%.*]] = fadd fast double [[MUL5_NEG]], [[SUB]]
176 ; CHECK-NEXT: [[FACTOR:%.*]] = fmul fast double [[SUB1]], 2.000000e+00
/external/llvm/test/CodeGen/AMDGPU/
Dlocal-memory-two-objects.ll47 ; SI-DAG: v_sub_i32_e32 [[SUB1:v[0-9]+]], vcc, 12, [[ADDRW]]
50 ; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[SUB1]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dlocal-memory.amdgcn.ll53 ; SI-DAG: v_sub_i32_e32 [[SUB1:v[0-9]+]], vcc, 12, [[ADDRW]]
56 ; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[SUB1]]
Dsminmax.v2i16.ll109 ; GFX9-DAG: v_pk_sub_i16 [[SUB1:v[0-9]+]], 0, s[[VAL1]]
111 ; GFX9-DAG: v_pk_max_i16 [[MAX1:v[0-9]+]], s[[VAL1]], [[SUB1]]
138 ; GFX9-DAG: v_pk_sub_i16 [[SUB1:v[0-9]+]], 0, v[[VAL1]]
139 ; GFX9-DAG: v_pk_max_i16 [[MAX1:v[0-9]+]], v[[VAL1]], [[SUB1]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dfmul.ll161 ; CHECK-NEXT: [[SUB1:%.*]] = fsub float -0.000000e+00, [[X:%.*]]
162 ; CHECK-NEXT: [[MUL:%.*]] = fmul float [[SUB1]], [[Y:%.*]]
163 ; CHECK-NEXT: [[MUL2:%.*]] = fmul float [[MUL]], [[SUB1]]
Dicmp.ll2182 ; CHECK-NEXT: [[SUB1:%.*]] = sub i32 %X, %Y
2183 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SUB]], [[SUB1]]
/external/pcre/dist2/src/
Dpcre2test.c1475 #define SUB1(a,b) \ macro
1928 #define SUB1(a,b) \ macro
2052 #define SUB1(a,b) G(a,8)(G(b,8)) macro
2156 #define SUB1(a,b) G(a,16)(G(b,16)) macro
2260 #define SUB1(a,b) G(a,32)(G(b,32)) macro
4875 SUB1(pcre2_code_free, compiled_code); in process_command()
5618 { SUB1(pcre2_code_free, compiled_code); } in process_pattern()
5644 SUB1(pcre2_code_free, compiled_code); in process_pattern()
8643 SUB1(pcre2_code_free, compiled_code); in main()
8737 SUB1(pcre2_code_free, compiled_code); in main()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/X86/
Dvect_copyable_in_binops.ll257 ; CHECK-NEXT: [[SUB1:%.*]] = sub nsw i32 [[TMP1]], -1
259 ; CHECK-NEXT: store i32 [[SUB1]], i32* [[INCDEC_PTR1]], align 4
667 ; CHECK-NEXT: [[SUB1:%.*]] = fsub fast float [[TMP1]], -1.000000e+00
669 ; CHECK-NEXT: store float [[SUB1]], float* [[INCDEC_PTR1]], align 4
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/
DARCInstrInfo.td225 defm SUB1 : ArcBinaryGEN4Inst<0b010111, "sub1">;
/external/llvm/test/Transforms/InstCombine/
Dicmp.ll1533 ; CHECK-NEXT: [[SUB1:%.*]] = sub i32 %X, %Y
1534 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SUB]], [[SUB1]]