| /external/mesa3d/src/gallium/docs/source/drivers/openswr/ |
| D | faq.rst | 26 SWR is a tile based immediate mode renderer with a sort-free threading
38 shader and fragment shaders, streamout, and fragment blending. SWR
72 of writing. Core SWR undergoes rigorous unit testing and we are quite
77 and SWR. Fixing these issues is one of our major future development
100 * Features - core SWR has a lot of functionality we have yet to
132 * You don't need a fire-breathing Xeon machine to work on SWR - we do
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| D | usage.rst | 43 SWR detected AVX2
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| /external/tcpdump/tests/ |
| D | pimv2_sm-v.out | 20 joined source #1: 1.1.1.1(SWR)
54 joined source #1: 1.1.1.1(SWR)
90 joined source #1: 1.1.1.1(SWR)
124 joined source #1: 1.1.1.1(SWR)
160 joined source #1: 1.1.1.1(SWR)
196 joined source #1: 1.1.1.1(SWR)
230 joined source #1: 1.1.1.1(SWR)
266 joined source #1: 1.1.1.1(SWR)
286 pruned source #1: 1.1.1.1(SWR)
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| /external/mesa3d/src/gallium/drivers/swr/ |
| D | meson.build | 190 error('Cannot find AVX support for swr. (these are required for SWR an all architectures.)')
289 error('SWR configured, but no SWR architectures configured')
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| D | SConscript | 246 # main SWR lib
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/ |
| D | unaligned-memops.ll | 18 ; MIPS: SWR [[LWR]], [[COPY]], 3 :: (store 4 into %ir.b, align 1)
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| D | unaligned-memops-mapping.mir | 63 SWR %4, %1, 3 :: (store 4 into %ir.b, align 1)
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 233 case Mips::SWR: in isBasePlusOffsetMemoryAccess()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 242 case Mips::SWR: in isBasePlusOffsetMemoryAccess()
|
| /external/mesa3d/src/gallium/ |
| D | meson.build | 45 error('SWR requires meson 0.44.0 or greater.')
|
| /external/u-boot/arch/arm/include/asm/arch-mx5/ |
| D | imx-regs.h | 134 #define SWR (1 << 1) macro
|
| /external/v8/src/mips/ |
| D | constants-mips.h | 469 SWR = ((5U << 3) + 6) << kOpcodeShift, enumerator
1272 OpcodeToBitNumber(SWL) | OpcodeToBitNumber(SW) | OpcodeToBitNumber(SWR) |
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| D | disasm-mips.cc | 1944 case SWR: in DecodeTypeImmediate()
|
| /external/v8/src/mips64/ |
| D | constants-mips64.h | 447 SWR = ((5U << 3) + 6) << kOpcodeShift, enumerator
1308 OpcodeToBitNumber(SWR) | OpcodeToBitNumber(SDR) |
|
| D | disasm-mips64.cc | 2224 case SWR: in DecodeTypeImmediate()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.h | 205 SWR, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrHFP.td | 165 def SWR : BinaryRR<"swr", 0x2F, null_frag, FP64, FP64>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | CodeGenSchedule.cpp | 1587 for (Record *SWR : SWRDefs) { in collectProcResources()
1588 Record *ModelDef = SWR->getValueAsDef("SchedModel"); in collectProcResources()
1589 addWriteRes(SWR, getProcModel(ModelDef).Index); in collectProcResources()
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/ |
| D | MBlazeDisassembler.cpp | 400 case 0x1: return MBlaze::SWR; in decodeSW()
|
| /external/u-boot/arch/arm/include/asm/arch-imx/ |
| D | imx-regs.h | 126 #define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8) macro
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.h | 251 SWR, enumerator
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| D | MipsScheduleP5600.td | 131 SBE, SHE, SWE, SCE, SWL, SWR, SWLE, SWRE)>;
|
| /external/mesa3d/ |
| D | configure.ac | 2461 dnl Architectures to build SWR library for
2653 AC_MSG_ERROR([unknown SWR build architecture '$arch'])
3197 echo " SWR archs: $swr_archs (builtin)"
3199 echo " SWR archs: $swr_archs"
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| D | meson.build | 1034 …error('The following drivers requires LLVM: Radv, RadeonSI, SWR. One of these is enabled, but LLVM…
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeInstrInfo.td | 472 def SWR : StoreM<0x36, 0x200, "swr ">;
|