Home
last modified time | relevance | path

Searched refs:SYSCLK (Results 1 – 22 of 22) sorted by relevance

/external/u-boot/doc/
DREADME.mpc85xxcds150 XXXX1000 == CCB:SYSCLK 8:1
151 XXXX1010 == CCB:SYSCLK 10:1
184 XXXX0000 == CCB:SYSCLK 16:1
186 XXXX0010 == CCB:SYSCLK 2:1
187 XXXX0011 == CCB:SYSCLK 3:1
188 XXXX0100 == CCB:SYSCLK 4:1
189 XXXX0101 == CCB:SYSCLK 5:1
190 XXXX0110 == CCB:SYSCLK 6:1
192 XXXX1000 == CCB:SYSCLK 8:1
193 XXXX1001 == CCB:SYSCLK 9:1
[all …]
DREADME.b4860qds91 - IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK, DDRCLK1,2 and
/external/u-boot/board/freescale/mpc8610hpcd/
DREADME50 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
51 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
65 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
/external/u-boot/board/freescale/mpc8641hpcn/
DREADME30 SW1(6-8) = 001 CONFIG_SYS_SYSCLK = 000 :: SYSCLK = 33MHz
31 001 :: SYSCLK = 40MHz
167 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
168 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
182 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
/external/u-boot/board/freescale/mpc8544ds/
DREADME68 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
69 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
83 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
/external/u-boot/include/dt-bindings/clock/
Dmicrochip,clock.h14 #define SYSCLK 3 macro
/external/u-boot/board/freescale/mpc8572ds/
DREADME62 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
63 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
/external/u-boot/board/freescale/bsc9132qds/
DREADME75 (SYSCLK = 100MHz, DDRCLK = 100MHz)
77 (SYSCLK = 100MHz, DDRCLK = 133MHz)
/external/u-boot/board/freescale/t4qds/
DREADME54 Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion)
58 System and DDR clock (SYSCLK, “DDRCLK”)
/external/u-boot/board/sbc8548/
DREADME37 to reflect a different CCB:SYSCLK ratio]
246 D15 SYSCLK 66MHz 33MHz
/external/u-boot/board/freescale/t104xrdb/
DREADME115 - System and DDR clock (SYSCLK, “DDRCLK”)
147 - System and DDR clock (SYSCLK, “DDRCLK”)
/external/u-boot/board/freescale/ls1021aqds/
DREADME89 - System and DDR clock (SYSCLK, DDRCLK)
/external/u-boot/board/freescale/ls1021atwr/
DREADME88 - System and DDR clock (SYSCLK, DDRCLK)
/external/u-boot/board/avionic-design/common/
Dpinmux-config-tamonten-ng.h259 DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
260 DEFAULT_PINMUX(CLK_32K_IN, SYSCLK, NORMAL, NORMAL, INPUT),
/external/u-boot/board/freescale/t102xqds/
DREADME109 - Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion).
113 - System and DDR clock (SYSCLK, DDRCLK).
/external/u-boot/board/freescale/t1040qds/
DREADME74 - System and DDR clock (SYSCLK, “DDRCLK”)
/external/u-boot/arch/arm/mach-tegra/tegra114/
Dpinmux.c230 PIN(SYS_CLK_REQ_PZ5, SYSCLK, RSVD2, RSVD3, RSVD4),
/external/u-boot/board/nvidia/dalmore/
Dpinmux-config-dalmore.h220 DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
/external/u-boot/arch/arm/mach-tegra/tegra30/
Dpinmux.c225 PIN(SYS_CLK_REQ_PZ5, SYSCLK, RSVD2, RSVD3, RSVD4),
/external/u-boot/board/nvidia/cardhu/
Dpinmux-config-cardhu.h247 DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
/external/u-boot/board/toradex/colibri_t30/
Dpinmux-config-colibri_t30.h255 DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT),
/external/u-boot/board/toradex/apalis_t30/
Dpinmux-config-apalis_t30.h265 DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, INPUT),