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Searched refs:SchedClass (Results 1 – 25 of 35) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/MC/
DMCSchedule.cpp58 unsigned SchedClass) const { in computeInstrLatency()
59 const MCSchedClassDesc &SCDesc = *getSchedClassDesc(SchedClass); in computeInstrLatency()
71 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass(); in computeInstrLatency() local
72 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass); in computeInstrLatency()
78 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID); in computeInstrLatency()
79 SCDesc = getSchedClassDesc(SchedClass); in computeInstrLatency()
82 if (SchedClass) in computeInstrLatency()
114 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass(); in getReciprocalThroughput() local
115 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass); in getReciprocalThroughput()
124 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID); in getReciprocalThroughput()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonDepTimingClasses.h21 inline bool is_TC3x(unsigned SchedClass) { in is_TC3x() argument
22 switch (SchedClass) { in is_TC3x()
42 inline bool is_TC2early(unsigned SchedClass) { in is_TC2early() argument
43 switch (SchedClass) { in is_TC2early()
52 inline bool is_TC4x(unsigned SchedClass) { in is_TC4x() argument
53 switch (SchedClass) { in is_TC4x()
66 inline bool is_TC2(unsigned SchedClass) { in is_TC2() argument
67 switch (SchedClass) { in is_TC2()
91 inline bool is_TC1(unsigned SchedClass) { in is_TC1() argument
92 switch (SchedClass) { in is_TC1()
DHexagonInstrInfo.cpp2099 unsigned SchedClass = MI.getDesc().getSchedClass(); in isEarlySourceInstr() local
2100 return is_TC4x(SchedClass) || is_TC3x(SchedClass); in isEarlySourceInstr()
2291 unsigned SchedClass = MI.getDesc().getSchedClass(); in isLateResultInstr() local
2292 return !is_TC1(SchedClass); in isLateResultInstr()
2540 unsigned SchedClass = MI.getDesc().getSchedClass(); in isTC1() local
2541 return is_TC1(SchedClass); in isTC1()
2545 unsigned SchedClass = MI.getDesc().getSchedClass(); in isTC2() local
2546 return is_TC2(SchedClass); in isTC2()
2550 unsigned SchedClass = MI.getDesc().getSchedClass(); in isTC2Early() local
2551 return is_TC2early(SchedClass); in isTC2Early()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DTargetSchedule.cpp136 unsigned SchedClass = MI->getDesc().getSchedClass(); in resolveSchedClass() local
137 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass); in resolveSchedClass()
147 SchedClass = STI->resolveSchedClass(SchedClass, MI, this); in resolveSchedClass()
148 SCDesc = SchedModel.getSchedClassDesc(SchedClass); in resolveSchedClass()
328 unsigned SchedClass = MI->getDesc().getSchedClass(); in computeReciprocalThroughput() local
329 return MCSchedModel::getReciprocalThroughput(SchedClass, in computeReciprocalThroughput()
341 unsigned SchedClass = TII->get(Opcode).getSchedClass(); in computeReciprocalThroughput() local
343 return MCSchedModel::getReciprocalThroughput(SchedClass, in computeReciprocalThroughput()
346 const MCSchedClassDesc &SCDesc = *SchedModel.getSchedClassDesc(SchedClass); in computeReciprocalThroughput()
/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-exegesis/lib/
DAnalysis.h52 struct SchedClass { struct
53 SchedClass(const llvm::MCSchedClassDesc &SD,
78 measurementsMatch(const llvm::MCSubtargetInfo &STI, const SchedClass &SC, argument
95 const SchedClass &SC,
97 void printSchedClassDescHtml(const SchedClass &SC,
DAnalysis.cpp242 const std::vector<SchedClassCluster> &Clusters, const SchedClass &SC, in printSchedClassClustersHtml()
375 Analysis::SchedClass::SchedClass(const llvm::MCSchedClassDesc &SD, in SchedClass() function in exegesis::Analysis::SchedClass
397 const llvm::MCSubtargetInfo &STI, const SchedClass &SC, in measurementsMatch()
450 void Analysis::printSchedClassDescHtml(const SchedClass &SC, in printSchedClassDescHtml()
591 const SchedClass SC(*SCDesc, *SubtargetInfo_); in run()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZHazardRecognizer.h123 if (!SU->SchedClass && SchedModel->hasInstrSchedModel()) in getSchedClass()
124 SU->SchedClass = SchedModel->resolveSchedClass(SU->getInstr()); in getSchedClass()
125 return SU->SchedClass; in getSchedClass()
/external/llvm/lib/CodeGen/
DTargetSchedule.cpp105 unsigned SchedClass = MI->getDesc().getSchedClass(); in resolveSchedClass() local
106 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass); in resolveSchedClass()
116 SchedClass = STI->resolveSchedClass(SchedClass, MI, this); in resolveSchedClass()
117 SCDesc = SchedModel.getSchedClassDesc(SchedClass); in resolveSchedClass()
/external/llvm/include/llvm/CodeGen/
DScheduleDAGInstrs.h247 if (!SU->SchedClass && SchedModel.hasInstrSchedModel()) in getSchedClass()
248 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr()); in getSchedClass()
249 return SU->SchedClass; in getSchedClass()
DScheduleDAG.h255 const MCSchedClassDesc *SchedClass; // NULL or resolved SchedClass.
309 : Node(node), Instr(nullptr), OrigNode(nullptr), SchedClass(nullptr),
325 : Node(nullptr), Instr(instr), OrigNode(nullptr), SchedClass(nullptr),
340 : Node(nullptr), Instr(nullptr), OrigNode(nullptr), SchedClass(nullptr),
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DScheduleDAGInstrs.h261 if (!SU->SchedClass && SchedModel.hasInstrSchedModel()) in getSchedClass()
262 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr()); in getSchedClass()
263 return SU->SchedClass; in getSchedClass()
DTargetSubtargetInfo.h141 virtual unsigned resolveSchedClass(unsigned SchedClass, in resolveSchedClass() argument
/external/swiftshader/third_party/LLVM/include/llvm/MC/
DMCInstrDesc.h138 unsigned short SchedClass; // enum identifying instr sched class variable
270 return SchedClass; in getSchedClass()
/external/llvm/include/llvm/MC/
DMCInstrDesc.h144 unsigned short SchedClass; // enum identifying instr sched class variable
528 unsigned getSchedClass() const { return SchedClass; } in getSchedClass()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/
DMCInstrDesc.h168 unsigned short SchedClass; // enum identifying instr sched class variable
570 unsigned getSchedClass() const { return SchedClass; } in getSchedClass()
DMCSubtargetInfo.h164 resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, in resolveVariantSchedClass() argument
DMCSchedule.h370 getReciprocalThroughput(unsigned SchedClass, const InstrItineraryData &IID);
/external/capstone/
DMCInstrDesc.h127 unsigned short SchedClass; // enum identifying instr sched class member
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCInstrInfo.cpp404 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); in getUnits() local
405 return ((II[SchedClass].FirstStage + HexagonStages)->getUnits()); in getUnits()
415 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); in getOtherReservedSlots() local
421 for (unsigned Stage = II[SchedClass].FirstStage + 1; in getOtherReservedSlots()
422 Stage < II[SchedClass].LastStage; ++Stage) { in getOtherReservedSlots()
/external/llvm/include/llvm/Target/
DTargetSubtargetInfo.h117 virtual unsigned resolveSchedClass(unsigned SchedClass, in resolveSchedClass() argument
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCInstrInfo.cpp380 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); in getUnits() local
381 return ((II[SchedClass].FirstStage + HexagonStages)->getUnits()); in getUnits()
728 unsigned SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); in prefersSlot3() local
729 switch (SchedClass) { in prefersSlot3()
/external/llvm/utils/TableGen/
DSubtargetEmitter.cpp1128 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx); in EmitSchedClassTables() local
1129 OS << " {DBGFIELD(\"" << SchedClass.Name << "\") "; in EmitSchedClassTables()
1130 if (SchedClass.Name.size() < 18) in EmitSchedClassTables()
1131 OS.indent(18 - SchedClass.Name.size()); in EmitSchedClassTables()
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.cpp2041 unsigned SchedClass = MI->getDesc().getSchedClass(); in isEarlySourceInstr() local
2042 if (SchedClass == Hexagon::Sched::M_tc_3or4x_SLOT23) in isEarlySourceInstr()
2251 unsigned SchedClass = MI->getDesc().getSchedClass(); in isLateResultInstr() local
2253 switch (SchedClass) { in isLateResultInstr()
2548 unsigned SchedClass = MI->getDesc().getSchedClass(); in isTC1() local
2549 switch (SchedClass) { in isTC1()
2567 unsigned SchedClass = MI->getDesc().getSchedClass(); in isTC2() local
2568 switch (SchedClass) { in isTC2()
2584 unsigned SchedClass = MI->getDesc().getSchedClass(); in isTC2Early() local
2585 switch (SchedClass) { in isTC2Early()
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/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DSubtargetEmitter.cpp1325 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx); in EmitSchedClassTables() local
1326 OS << " {DBGFIELD(\"" << SchedClass.Name << "\") "; in EmitSchedClassTables()
1327 if (SchedClass.Name.size() < 18) in EmitSchedClassTables()
1328 OS.indent(18 - SchedClass.Name.size()); in EmitSchedClassTables()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenSubtargetInfo.inc2437 unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
2456 unsigned resolveVariantSchedClass(unsigned SchedClass,
2458 return Mips_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
2544 unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
2550 …unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel…
2551 …unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const ove…
2577 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel…
2578 switch (SchedClass) {
2740 report_fatal_error("Expected a variant SchedClass");
2744 ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
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