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Searched refs:SchedRW (Results 1 – 25 of 67) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrSystem.td16 let SchedRW = [WriteSystem] in {
38 } // SchedRW
44 let SchedRW = [WriteSystem] in {
60 } // SchedRW
70 let SchedRW = [WriteSystem] in {
109 } // SchedRW
114 let SchedRW = [WriteSystem] in {
128 } // SchedRW
133 let SchedRW = [WriteSystem] in {
147 } // SchedRW
[all …]
DX86InstrFPStack.td244 let SchedRW = [WriteFAddLd] in {
250 let SchedRW = [WriteFMulLd] in {
254 let SchedRW = [WriteFDivLd] in {
270 let SchedRW = [WriteFAdd] in {
280 } // SchedRW
281 let SchedRW = [WriteFCom] in {
284 } // SchedRW
285 let SchedRW = [WriteFMul] in {
289 } // SchedRW
290 let SchedRW = [WriteFDiv] in {
[all …]
DX86InstrTSX.td21 let SchedRW = [WriteSystem] in {
50 } // SchedRW
53 let SchedRW = [WriteSystem] in {
60 } // SchedRW
DX86InstrInfo.td1156 let hasSideEffects = 0, SchedRW = [WriteNop] in {
1180 let SchedRW = [WriteALU] in {
1188 } // SchedRW
1195 SchedRW = [WriteSystem] in
1200 let mayLoad = 1, SchedRW = [WriteLoad] in {
1212 } // mayLoad, SchedRW
1213 let mayStore = 1, mayLoad = 1, SchedRW = [WriteRMW] in {
1220 let mayStore = 1, SchedRW = [WriteStore] in {
1244 } // mayStore, SchedRW
1246 let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in {
[all …]
DX86InstrShiftRotate.td18 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
65 } // Constraints = "$src = $dst", SchedRW
68 let SchedRW = [WriteShiftLd, WriteRMW] in {
120 } // SchedRW
122 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
166 } // Constraints = "$src = $dst", SchedRW
169 let SchedRW = [WriteShiftLd, WriteRMW] in {
219 } // SchedRW
221 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
268 } // Constraints = "$src = $dst", SchedRW
[all …]
DX86InstrSGX.td18 let SchedRW = [WriteSystem], Predicates = [HasSGX] in {
30 } // SchedRW
DX86InstrControl.td23 hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in {
62 let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
74 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in {
105 let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in {
192 let SchedRW = [WriteJump] in {
270 isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in
295 isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in
313 let isCall = 1, Uses = [RSP, SSP], SchedRW = [WriteJump] in {
345 isCodeGenOnly = 1, Uses = [RSP, SSP], SchedRW = [WriteJump] in {
379 SchedRW = [WriteJump] in {
[all …]
DX86InstrMMX.td28 isPseudo = 1, SchedRW = [WriteZero] in {
156 let SchedRW = [WriteEMMS] in
212 let SchedRW = [WriteVecMove], hasSideEffects = 0, isMoveReg = 1 in {
219 } // SchedRW, hasSideEffects, isMoveReg
231 let SchedRW = [SchedWriteVecMoveLS.MMX.RM] in {
236 } // SchedRW
238 let SchedRW = [SchedWriteVecMoveLS.MMX.MR] in
243 let SchedRW = [SchedWriteVecMoveLS.XMM.RR] in {
267 } // SchedRW
580 let SchedRW = [SchedWriteShuffle.MMX] in {
DX86InstrSVM.td18 let SchedRW = [WriteSystem] in {
63 } // SchedRW
DX86ScheduleBtVer2.td101 multiclass JWriteResIntPair<X86FoldableSchedWrite SchedRW,
105 def : WriteRes<SchedRW, ExePorts> {
113 def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> {
120 multiclass JWriteResFpuPair<X86FoldableSchedWrite SchedRW,
124 def : WriteRes<SchedRW, ExePorts> {
132 def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> {
139 multiclass JWriteResYMMPair<X86FoldableSchedWrite SchedRW,
143 def : WriteRes<SchedRW, ExePorts> {
151 def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> {
DX86InstrCompiler.td36 SchedRW = [WriteJump] in
41 let hasSideEffects = 0, mayLoad = 1, isNotDuplicable = 1, SchedRW = [WriteJump] in
50 let Defs = [ESP, EFLAGS, SSP], Uses = [ESP, SSP], SchedRW = [WriteALU] in {
68 let Defs = [RSP, EFLAGS, SSP], Uses = [RSP, SSP], SchedRW = [WriteALU] in {
80 let SchedRW = [WriteSystem] in {
146 } // SchedRW
163 let SchedRW = [WriteSystem] in {
229 } // SchedRW
234 let isPseudo = 1, SchedRW = [WriteSystem] in {
260 let isPseudo = 1, SchedRW = [WriteJumpLd] in {
[all …]
DX86InstrCMovSetCC.td20 isCommutable = 1, SchedRW = [Sched] in {
41 SchedRW = [Sched.Folded, ReadAfterLd] in {
114 let Uses = [EFLAGS], Defs = [AL], SchedRW = [WriteALU] in {
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DVOP1Instructions.td137 // FIXME: Specify SchedRW for READFIRSTLANE_B32
169 let SchedRW = [WriteQuarterRate32] in {
189 } // End SchedRW = [WriteQuarterRate32]
197 let SchedRW = [WriteQuarterRate32] in {
204 } // End SchedRW = [WriteQuarterRate32]
206 let SchedRW = [WriteDouble] in {
209 } // End SchedRW = [WriteDouble];
211 let SchedRW = [WriteDouble] in {
213 } // End SchedRW = [WriteDouble]
215 let SchedRW = [WriteQuarterRate32] in {
[all …]
DVOP3Instructions.td293 let SchedRW = [WriteDoubleAdd] in {
299 } // End SchedRW = [WriteDoubleAdd]
301 let SchedRW = [WriteQuarterRate32] in {
306 } // End SchedRW = [WriteQuarterRate32]
316 let SchedRW = [WriteFloatFMA];
325 let SchedRW = [WriteDouble];
356 let SchedRW = [WriteDoubleAdd] in {
359 } // End SchedRW = [WriteDoubleAdd]
362 let SchedRW = [WriteFloatFMA, WriteSALU];
368 let SchedRW = [WriteDouble, WriteSALU];
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DCodeGenSchedule.cpp514 const CodeGenSchedRW &SchedRW = getSchedRW(RWIdx, IsRead); in expandRWSequence() local
515 if (!SchedRW.IsSequence) { in expandRWSequence()
520 SchedRW.TheDef ? SchedRW.TheDef->getValueAsInt("Repeat") : 1; in expandRWSequence()
522 for (unsigned I : SchedRW.Sequence) { in expandRWSequence()
592 CodeGenSchedRW SchedRW(RWIdx, IsRead, Seq, genRWName(Seq, IsRead)); in findOrInsertRW() local
593 RWVec.push_back(SchedRW); in findOrInsertRW()
1072 const CodeGenSchedRW &SchedRW, unsigned TransIdx,
1094 const CodeGenSchedRW &SchedRW = SchedModels.getSchedRW(PC.RWIdx, PC.IsRead); in mutuallyExclusive() local
1095 assert(SchedRW.HasVariants && "PredCheck must refer to a SchedVariant"); in mutuallyExclusive()
1096 RecVec Variants = SchedRW.TheDef->getValueAsListOfDefs("Variants"); in mutuallyExclusive()
[all …]
/external/llvm/utils/TableGen/
DCodeGenSchedule.cpp403 const CodeGenSchedRW &SchedRW = getSchedRW(RWIdx, IsRead); in expandRWSequence() local
404 if (!SchedRW.IsSequence) { in expandRWSequence()
409 SchedRW.TheDef ? SchedRW.TheDef->getValueAsInt("Repeat") : 1; in expandRWSequence()
411 for (IdxIter I = SchedRW.Sequence.begin(), E = SchedRW.Sequence.end(); in expandRWSequence()
485 CodeGenSchedRW SchedRW(RWIdx, IsRead, Seq, genRWName(Seq, IsRead)); in findOrInsertRW() local
487 SchedReads.push_back(SchedRW); in findOrInsertRW()
489 SchedWrites.push_back(SchedRW); in findOrInsertRW()
968 const CodeGenSchedRW &SchedRW, unsigned TransIdx,
991 const CodeGenSchedRW &SchedRW = SchedModels.getSchedRW(I->RWIdx, I->IsRead); in mutuallyExclusive() local
992 assert(SchedRW.HasVariants && "PredCheck must refer to a SchedVariant"); in mutuallyExclusive()
[all …]
/external/llvm/lib/Target/X86/
DX86InstrSystem.td16 let SchedRW = [WriteSystem] in {
39 } // SchedRW
45 let SchedRW = [WriteSystem] in {
63 } // SchedRW
73 let SchedRW = [WriteSystem] in {
114 } // SchedRW
119 let SchedRW = [WriteSystem] in {
133 } // SchedRW
138 let SchedRW = [WriteSystem] in {
152 } // SchedRW
[all …]
DX86InstrFPStack.td243 let SchedRW = [WriteFAddLd] in {
248 let SchedRW = [WriteFMulLd] in {
251 let SchedRW = [WriteFDivLd] in {
267 let SchedRW = [WriteFAdd] in {
277 } // SchedRW
278 let SchedRW = [WriteFMul] in {
282 } // SchedRW
283 let SchedRW = [WriteFDiv] in {
290 } // SchedRW
309 let SchedRW = [WriteFSqrt] in {
[all …]
DX86InstrInfo.td1059 let hasSideEffects = 0, SchedRW = [WriteZero] in {
1072 let SchedRW = [WriteALU] in {
1082 } // SchedRW
1093 let mayLoad = 1, SchedRW = [WriteLoad] in {
1106 } // mayLoad, SchedRW
1108 let mayStore = 1, SchedRW = [WriteStore] in {
1129 } // mayStore, SchedRW
1131 let mayLoad = 1, mayStore = 1, SchedRW = [WriteRMW] in {
1136 } // mayLoad, mayStore, SchedRW
1141 SchedRW = [WriteRMW], Defs = [ESP] in {
[all …]
DX86InstrArithmetic.td17 let SchedRW = [WriteLEA] in {
39 } // SchedRW
154 let isCommutable = 1, SchedRW = [WriteIMul] in {
173 } // isCommutable, SchedRW
176 let SchedRW = [WriteIMulLd, ReadAfterLd] in {
198 } // SchedRW
205 let SchedRW = [WriteIMul] in {
243 } // SchedRW
246 let SchedRW = [WriteIMulLd] in {
288 } // SchedRW
[all …]
DX86InstrShiftRotate.td18 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
66 } // Constraints = "$src = $dst", SchedRW
69 let SchedRW = [WriteShiftLd, WriteRMW] in {
122 } // SchedRW
124 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
168 } // Constraints = "$src = $dst", SchedRW
171 let SchedRW = [WriteShiftLd, WriteRMW] in {
222 } // SchedRW
224 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
279 } // Constraints = "$src = $dst", SchedRW
[all …]
DX86ScheduleBtVer2.td77 multiclass JWriteResIntPair<X86FoldableSchedWrite SchedRW,
81 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
85 def : WriteRes<SchedRW.Folded, [JLAGU, ExePort]> {
90 multiclass JWriteResFpuPair<X86FoldableSchedWrite SchedRW,
94 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
98 def : WriteRes<SchedRW.Folded, [JLAGU, ExePort]> {
DX86InstrControl.td23 hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in {
72 let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
84 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in {
115 let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in {
180 let SchedRW = [WriteJump] in {
244 isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in
275 let isCall = 1, Uses = [RSP], SchedRW = [WriteJump] in {
298 SchedRW = [WriteJump] in {
/external/llvm/lib/Target/AMDGPU/
DSIInstrFormats.td85 let SchedRW = [Write32Bit];
281 let SchedRW = [WriteSALU] in {
343 } // let SchedRW = [WriteSALU]
354 let SchedRW = [WriteSMEM];
683 let SchedRW = [WriteLDS];
697 let SchedRW = [WriteVMEM];
710 let SchedRW = [WriteVMEM];
726 let SchedRW = [WriteVMEM];
DCIInstructions.td34 let SchedRW = [WriteDoubleAdd] in {
47 } // End SchedRW = [WriteDoubleAdd]
49 let SchedRW = [WriteQuarterRate32] in {
56 } // End SchedRW = [WriteQuarterRate32]

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