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Searched refs:Scheduling (Results 1 – 25 of 188) sorted by relevance

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/external/llvm/test/CodeGen/AArch64/
Darm64-ldp-cluster.ll6 ; CHECK: ********** MI Scheduling **********
11 ; EXYNOS: ********** MI Scheduling **********
26 ; CHECK: ********** MI Scheduling **********
31 ; EXYNOS: ********** MI Scheduling **********
47 ; CHECK: ********** MI Scheduling **********
52 ; EXYNOS: ********** MI Scheduling **********
67 ; CHECK: ********** MI Scheduling **********
72 ; EXYNOS: ********** MI Scheduling **********
90 ; CHECK: ********** MI Scheduling **********
95 ; EXYNOS: ********** MI Scheduling **********
[all …]
Daarch64-stp-cluster.ll4 ; CHECK: ********** MI Scheduling **********
25 ; CHECK: ********** MI Scheduling **********
46 ; CHECK:********** MI Scheduling **********
67 ; CHECK:********** MI Scheduling **********
88 ; CHECK:********** MI Scheduling **********
109 ; CHECK:********** MI Scheduling **********
130 ; CHECK: ********** MI Scheduling **********
Darm64-misched-basic-A53.ll9 ; CHECK: ********** MI Scheduling **********
85 ; CHECK: ********** MI Scheduling **********
131 ; CHECK: ********** MI Scheduling **********
179 ; CHECK: ********** MI Scheduling **********
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-ldp-cluster.ll7 ; CHECK: ********** MI Scheduling **********
12 ; EXYNOSM1: ********** MI Scheduling **********
27 ; CHECK: ********** MI Scheduling **********
32 ; EXYNOSM1: ********** MI Scheduling **********
48 ; CHECK: ********** MI Scheduling **********
53 ; EXYNOSM1: ********** MI Scheduling **********
68 ; CHECK: ********** MI Scheduling **********
73 ; EXYNOSM1: ********** MI Scheduling **********
91 ; CHECK: ********** MI Scheduling **********
96 ; EXYNOSM1: ********** MI Scheduling **********
[all …]
Daarch64-stp-cluster.ll4 ; CHECK: ********** MI Scheduling **********
25 ; CHECK: ********** MI Scheduling **********
46 ; CHECK:********** MI Scheduling **********
67 ; CHECK:********** MI Scheduling **********
88 ; CHECK:********** MI Scheduling **********
109 ; CHECK:********** MI Scheduling **********
130 ; CHECK: ********** MI Scheduling **********
Darm64-misched-basic-A53.ll9 ; CHECK: ********** MI Scheduling **********
85 ; CHECK: ********** MI Scheduling **********
131 ; CHECK: ********** MI Scheduling **********
179 ; CHECK: ********** MI Scheduling **********
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dcortex-a57-misched-alu.ll7 ; CHECK: ********** MI Scheduling **********
35 ; CHECK: Scheduling
41 ; CHECK: Scheduling
47 ; CHECK: Scheduling
53 ; CHECK: Scheduling
59 ; CHECK: Scheduling
Dsingle-issue-r52.mir21 # CHECK: ********** MI Scheduling **********
33 # TOPDOWN: Scheduling SU(1) %1:qqpr = VLD4d8Pseudo
35 # TOPDOWN: Scheduling SU(2) %4:dpr = VADDv8i8
37 # BOTTOMUP: Scheduling SU(2) %4:dpr = VADDv8i8
38 # BOTTOMUP: Scheduling SU(1) %1:qqpr = VLD4d8Pseudo
Dcortex-a57-misched-vfma.ll7 ; CHECK: ********** MI Scheduling **********
46 ; CHECK: ********** MI Scheduling **********
84 ; CHECK: ********** MI Scheduling **********
123 ; CHECK: ********** MI Scheduling **********
161 ; CHECK: ********** MI Scheduling **********
180 ; CHECK: ********** MI Scheduling **********
Dcortex-a57-misched-vstm.ll4 ; CHECK: ********** MI Scheduling **********
6 ; CHECK: ********** MI Scheduling **********
Dcortex-a57-misched-ldm.ll4 ; CHECK: ********** MI Scheduling **********
6 ; CHECK: ********** MI Scheduling **********
Dcortex-a57-misched-vldm.ll4 ; CHECK: ********** MI Scheduling **********
6 ; CHECK: ********** MI Scheduling **********
Dcortex-a57-misched-stm.ll5 ; CHECK: ********** MI Scheduling **********
7 ; CHECK: ********** MI Scheduling **********
Dcortex-a57-misched-stm-wrback.ll5 ; CHECK: ********** MI Scheduling **********
7 ; CHECK: ********** MI Scheduling **********
Dcortex-a57-misched-ldm-wrback.ll9 ; CHECK: ********** MI Scheduling **********
11 ; CHECK: ********** MI Scheduling **********
Dcortex-a57-misched-vstm-wrback.ll4 ; CHECK: ********** MI Scheduling **********
6 ; CHECK: ********** MI Scheduling **********
D2012-06-12-SchedMemLatency.ll7 ; CHECK: ** List Scheduling
17 ; CHECK: ** List Scheduling
Dcortex-a57-misched-vldm-wrback.ll9 ; CHECK: ********** MI Scheduling **********
11 ; CHECK: ********** MI Scheduling **********
/external/llvm/test/CodeGen/ARM/
D2012-06-12-SchedMemLatency.ll7 ; CHECK: ** List Scheduling
17 ; CHECK: ** List Scheduling
/external/syzkaller/pkg/gce/
Dgce.go133 Scheduling: &compute.Scheduling{
150 if _, ok := err.(resourcePoolExhaustedError); ok && instance.Scheduling.Preemptible {
151 instance.Scheduling.Preemptible = false
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Generic/
Dopt-codegen-no-target-machine.ll3 ; CHECK: Trying to construct TargetPassConfig without a target machine. Scheduling a CodeGen pass w…
/external/ltp/testcases/open_posix_testsuite/conformance/interfaces/pthread_rwlock_rdlock/
Dcoverage.txt5 2 YES ** Need support of Threads Execution Scheduling
/external/ltp/testcases/open_posix_testsuite/conformance/interfaces/mq_send/
Dcoverage.txt9 6 WON'T - will not test as needs Priority Scheduling to finish
/external/llvm/lib/Target/Hexagon/
DHexagonSchedule.td1 //===- HexagonSchedule.td - Hexagon Scheduling Definitions -*- tablegen -*-===//
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMScheduleM3.td1 //=- ARMScheduleM3.td - ARM Cortex-M3 Scheduling Definitions -*- tablegen -*-=//

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