Home
last modified time | relevance | path

Searched refs:Scl (Results 1 – 10 of 10) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrFMA.td322 SchedWriteFMA.Scl>, VEX_LIG;
324 SchedWriteFMA.Scl>, VEX_LIG;
327 SchedWriteFMA.Scl>, VEX_LIG;
329 SchedWriteFMA.Scl>, VEX_LIG;
538 SchedWriteFMA.Scl>,
540 SchedWriteFMA.Scl>;
542 SchedWriteFMA.Scl>,
544 SchedWriteFMA.Scl>;
546 X86Fnmadd, loadf32, SchedWriteFMA.Scl>,
548 SchedWriteFMA.Scl>;
[all …]
DX86InstrXOP.td79 ssmem, sse_load_f32, SchedWriteFRnd.Scl>;
88 sdmem, sse_load_f64, SchedWriteFRnd.Scl>;
DX86InstrAVX512.td2133 SchedWriteFCmp.Scl>, AVX512XSIi8Base;
2136 SchedWriteFCmp.Scl>, AVX512XDIi8Base, VEX_W;
2796 sched.Scl, f32x_info, prd>,
2799 sched.Scl, f64x_info, prd>,
5236 sched.PS.Scl, IsCommutable>,
5238 sched.PS.Scl, IsCommutable>,
5241 sched.PD.Scl, IsCommutable>,
5243 sched.PD.Scl, IsCommutable>,
5251 VecNode, SaeNode, sched.PS.Scl, IsCommutable>,
5254 VecNode, SaeNode, sched.PD.Scl, IsCommutable>,
[all …]
DX86Schedule.td70 X86FoldableSchedWrite Scl = sScl; // Scalar float/double operations.
98 X86SchedWriteMoveLS Scl = sScl; // Scalar float/double operations.
DX86InstrSSE.td1847 SchedWriteFCmpSizes.PS.Scl>, XS, VEX_4V, VEX_LIG, VEX_WIG;
1852 SchedWriteFCmpSizes.PD.Scl>,
1860 SchedWriteFCmpSizes.PS.Scl>, XS;
1865 SchedWriteFCmpSizes.PD.Scl>, XD;
1889 SchedWriteFCmpSizes.PS.Scl, sse_load_f32>, XS, VEX_4V;
1893 SchedWriteFCmpSizes.PD.Scl, sse_load_f64>,
1899 SchedWriteFCmpSizes.PS.Scl, sse_load_f32>, XS;
1903 SchedWriteFCmpSizes.PD.Scl, sse_load_f64>, XD;
2550 OpNode, FR32, f32mem, SSEPackedSingle, sched.PS.Scl, 0>,
2553 OpNode, FR64, f64mem, SSEPackedDouble, sched.PD.Scl, 0>,
[all …]
DX86ISelLowering.cpp30737 SDValue Scl = DAG.getNode(Opcode1, DL, SVT, N10, N11); in combineTargetShuffle() local
30738 SDValue SclVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Scl); in combineTargetShuffle()
37652 SDValue Scl = DAG.getAnyExtOrTrunc(N00, DL, SVT); in combineToExtendBoolVectorInReg() local
37653 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Scl); in combineToExtendBoolVectorInReg()
/external/llvm/lib/Target/ARM/
DARMAsmPrinter.cpp140 COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC in runOnMachineFunction() local
145 OutStreamer->EmitCOFFSymbolStorageClass(Scl); in runOnMachineFunction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMAsmPrinter.cpp150 COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC in runOnMachineFunction() local
155 OutStreamer->EmitCOFFSymbolStorageClass(Scl); in runOnMachineFunction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp1504 SDValue Scl = Op.getOperand(1); in SimplifyDemandedVectorElts() local
1520 if (Scl.isUndef()) in SimplifyDemandedVectorElts()
1524 if (isNullConstant(Scl) || isNullFPConstant(Scl)) in SimplifyDemandedVectorElts()
/external/clang/lib/CodeGen/
DCGBuiltin.cpp7082 Value *Scl = Builder.CreateExtractElement(Ops[1], (uint64_t)0, "extract"); in EmitX86BuiltinExpr() local
7086 llvm::PointerType::getUnqual(Scl->getType()), in EmitX86BuiltinExpr()
7090 StoreInst *SI = Builder.CreateDefaultAlignedStore(Scl, BC); in EmitX86BuiltinExpr()