| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 2097 unsigned &SecondReg, in CanFormLdStDWord() argument
2159 SecondReg = Op1->getOperand(0).getReg(); in CanFormLdStDWord()
2160 if (FirstReg == SecondReg) in CanFormLdStDWord()
2263 unsigned FirstReg = 0, SecondReg = 0; in RescheduleOps() local
2271 FirstReg, SecondReg, BaseReg, in RescheduleOps()
2279 MRI->constrainRegClass(SecondReg, TRC); in RescheduleOps()
2285 .addReg(SecondReg, RegState::Define) in RescheduleOps()
2299 .addReg(SecondReg) in RescheduleOps()
2316 MRI->setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg); in RescheduleOps()
2317 MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg); in RescheduleOps()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 2058 unsigned &SecondReg, in CanFormLdStDWord() argument
2120 SecondReg = Op1->getOperand(0).getReg(); in CanFormLdStDWord()
2121 if (FirstReg == SecondReg) in CanFormLdStDWord()
2217 unsigned FirstReg = 0, SecondReg = 0; in RescheduleOps() local
2225 FirstReg, SecondReg, BaseReg, in RescheduleOps()
2233 MRI->constrainRegClass(SecondReg, TRC); in RescheduleOps()
2239 .addReg(SecondReg, RegState::Define) in RescheduleOps()
2253 .addReg(SecondReg) in RescheduleOps()
2270 MRI->setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg); in RescheduleOps()
2271 MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg); in RescheduleOps()
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 4651 int SecondReg = tryParseRegister(); in tryParseGPRSeqPair() local
4652 if (SecondReg ==-1) { in tryParseGPRSeqPair()
4656 if (RI->getEncodingValue(SecondReg) != FirstEncoding + 1 || in tryParseGPRSeqPair()
4657 (isXReg && !XRegClass.contains(SecondReg)) || in tryParseGPRSeqPair()
4658 (isWReg && !WRegClass.contains(SecondReg))) { in tryParseGPRSeqPair()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 5440 unsigned SecondReg; in tryParseGPRSeqPair() local
5441 Res = tryParseScalarRegister(SecondReg); in tryParseGPRSeqPair()
5445 if (RI->getEncodingValue(SecondReg) != FirstEncoding + 1 || in tryParseGPRSeqPair()
5446 (isXReg && !XRegClass.contains(SecondReg)) || in tryParseGPRSeqPair()
5447 (isWReg && !WRegClass.contains(SecondReg))) { in tryParseGPRSeqPair()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 792 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect() local
809 .addReg(FirstReg).addReg(SecondReg) in insertSelect()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 4116 unsigned SecondReg = Inst.getOperand(1).getReg(); in expandTrunc() local
4132 FirstReg, SecondReg, IDLoc, STI); in expandTrunc()
4140 FirstReg, SecondReg, IDLoc, STI); in expandTrunc()
4839 unsigned SecondReg = nextReg(FirstReg); in expandLoadStoreDMacro() local
4841 if (!SecondReg) in expandLoadStoreDMacro()
4860 TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI); in expandLoadStoreDMacro()
4862 TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI); in expandLoadStoreDMacro()
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringMIPS32.cpp | 1937 const auto SecondReg = in legalizeMov() local
1940 SrcGPRLo = Target->makeReg(IceType_i32, SecondReg); in legalizeMov()
2009 const auto SecondReg = in legalizeMov() local
2012 Variable *SrcGPRLo = Target->makeReg(IceType_i32, SecondReg); in legalizeMov()
2096 const auto SecondReg = in legalizeMov() local
2099 Variable *DstGPRLo = Target->makeReg(IceType_i32, SecondReg); in legalizeMov()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 844 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect() local
861 .addReg(FirstReg).addReg(SecondReg) in insertSelect()
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3140 unsigned SecondReg = Inst.getOperand(1).getReg(); in expandTrunc() local
3156 FirstReg, SecondReg, IDLoc, STI); in expandTrunc()
3164 FirstReg, SecondReg, IDLoc, STI); in expandTrunc()
|