Searched refs:SegmentReg (Results 1 – 7 of 7) sorted by relevance
| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstX8632.cpp | 79 uint16_t Shift, SegmentRegisters SegmentReg, bool IsRebased) in X86OperandMem() argument
81 Shift(Shift), SegmentReg(SegmentReg), IsRebased(IsRebased) { in X86OperandMem()
150 if (SegmentReg != DefaultSegment) { in emit()
151 assert(SegmentReg >= 0 && SegmentReg < SegReg_NUM); in emit()
152 Str << "%" << X8632::Traits::InstSegmentRegNames[SegmentReg] << ":"; in emit()
192 if (SegmentReg != DefaultSegment) { in dump()
193 assert(SegmentReg >= 0 && SegmentReg < SegReg_NUM); in dump()
194 Str << X8632::Traits::InstSegmentRegNames[SegmentReg] << ":"; in dump()
255 if (SegmentReg != DefaultSegment) { in emitSegmentOverride()
256 assert(SegmentReg >= 0 && SegmentReg < SegReg_NUM); in emitSegmentOverride()
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| D | IceTargetLoweringX8632Traits.h | 843 SegmentRegisters SegmentReg = DefaultSegment,
846 Func, Ty, Base, Offset, Index, Shift, SegmentReg, IsRebased);
859 SegmentRegisters getSegmentRegister() const { return SegmentReg; }
879 Variable *Index, uint16_t Shift, SegmentRegisters SegmentReg,
886 const SegmentRegisters SegmentReg : 16;
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| D | IceTargetLoweringX86BaseImpl.h | 5903 static constexpr auto SegmentReg =
5907 NewAddr.Index, NewAddr.Shift, SegmentReg);
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| /external/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 780 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg; in EmitNop() local
781 Opc = IndexReg = Displacement = SegmentReg = 0; in EmitNop()
800 IndexReg = X86::RAX; SegmentReg = X86::CS; break; in EmitNop()
825 .addReg(SegmentReg), in EmitNop()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 813 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg; in EmitNop() local
814 Opc = IndexReg = Displacement = SegmentReg = 0; in EmitNop()
872 SegmentReg = X86::CS; in EmitNop()
896 .addReg(SegmentReg), in EmitNop()
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| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | CodeGenerator.rst | 2178 SegmentReg: Base + [1,2,4,8] * IndexReg + Disp32
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| /external/llvm/docs/ |
| D | CodeGenerator.rst | 2167 SegmentReg: Base + [1,2,4,8] * IndexReg + Disp32
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