| /external/capstone/arch/ARM/ |
| D | ARMAddressingModes.h | 115 static inline unsigned getSORegOpc(ARM_AM_ShiftOpc ShOp, unsigned Imm) in getSORegOpc() argument
117 return ShOp | (Imm << 3); in getSORegOpc()
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| D | ARMDisassembler.c | 1623 ARM_AM_ShiftOpc ShOp; in DecodeSORegMemOperand() local
1631 ShOp = ARM_AM_lsl; in DecodeSORegMemOperand()
1634 ShOp = ARM_AM_lsl; in DecodeSORegMemOperand()
1637 ShOp = ARM_AM_lsr; in DecodeSORegMemOperand()
1640 ShOp = ARM_AM_asr; in DecodeSORegMemOperand()
1643 ShOp = ARM_AM_ror; in DecodeSORegMemOperand()
1647 if (ShOp == ARM_AM_ror && imm == 0) in DecodeSORegMemOperand()
1648 ShOp = ARM_AM_rrx; in DecodeSORegMemOperand()
1655 shift = ARM_AM_getAM2Opc(ARM_AM_add, imm, ShOp, 0); in DecodeSORegMemOperand()
1657 shift = ARM_AM_getAM2Opc(ARM_AM_sub, imm, ShOp, 0); in DecodeSORegMemOperand()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 111 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc() argument
112 return ShOp | (Imm << 3); in getSORegOpc()
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| D | ARMMCCodeEmitter.cpp | 900 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue() local
901 unsigned SBits = getShiftOp(ShOp); in getLdStSORegOpValue()
947 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); in getAddrMode2OffsetOpValue() local
949 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5] in getAddrMode2OffsetOpValue()
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 112 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc() argument
113 return ShOp | (Imm << 3); in getSORegOpc()
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| D | ARMMCCodeEmitter.cpp | 1076 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue() local
1077 unsigned SBits = getShiftOp(ShOp); in getLdStSORegOpValue()
1114 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); in getAddrMode2OffsetOpValue() local
1116 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5] in getAddrMode2OffsetOpValue()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 110 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc() argument
111 return ShOp | (Imm << 3); in getSORegOpc()
|
| D | ARMMCCodeEmitter.cpp | 1087 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue() local
1088 unsigned SBits = getShiftOp(ShOp); in getLdStSORegOpValue()
1125 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); in getAddrMode2OffsetOpValue() local
1127 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5] in getAddrMode2OffsetOpValue()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 1915 ValueType Ty, SDNode ShOp>
1920 (Ty (ShOp (Ty DPR:$Vn),
1925 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1930 (Ty (ShOp (Ty DPR:$Vn),
1955 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1960 (ResTy (ShOp (ResTy QPR:$Vn),
1966 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1971 (ResTy (ShOp (ResTy QPR:$Vn),
2073 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2080 (Ty (ShOp (Ty DPR:$src1),
[all …]
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 1539 SDValue ShOp = N->getOperand(1); in WidenVecRes_POWI() local
1540 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp); in WidenVecRes_POWI()
1546 SDValue ShOp = N->getOperand(1); in WidenVecRes_Shift() local
1548 EVT ShVT = ShOp.getValueType(); in WidenVecRes_Shift()
1550 ShOp = GetWidenedVector(ShOp); in WidenVecRes_Shift()
1551 ShVT = ShOp.getValueType(); in WidenVecRes_Shift()
1557 ShOp = ModifyToType(ShOp, ShWidenVT); in WidenVecRes_Shift()
1559 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp, ShOp); in WidenVecRes_Shift()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1761 CreateShiftExtend(AArch64_AM::ShiftExtendType ShOp, unsigned Val, in CreateShiftExtend() argument
1764 Op->ShiftExtend.Type = ShOp; in CreateShiftExtend()
2382 AArch64_AM::ShiftExtendType ShOp = in tryParseOptionalShiftExtend() local
2399 if (ShOp == AArch64_AM::InvalidShiftExtend) in tryParseOptionalShiftExtend()
2407 if (ShOp == AArch64_AM::LSL || ShOp == AArch64_AM::LSR || in tryParseOptionalShiftExtend()
2408 ShOp == AArch64_AM::ASR || ShOp == AArch64_AM::ROR || in tryParseOptionalShiftExtend()
2409 ShOp == AArch64_AM::MSL) { in tryParseOptionalShiftExtend()
2418 AArch64Operand::CreateShiftExtend(ShOp, 0, false, S, E, getContext())); in tryParseOptionalShiftExtend()
2445 ShOp, MCE->getValue(), true, S, E, getContext())); in tryParseOptionalShiftExtend()
|
| /external/swiftshader/third_party/LLVM/lib/Transforms/InstCombine/ |
| D | InstCombineMulDivRem.cpp | 117 if (Constant *ShOp = dyn_cast<Constant>(SI->getOperand(1))) in visitMul() local
119 ConstantExpr::getShl(CI, ShOp)); in visitMul()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 2572 ValueType Ty, SDNode ShOp>
2577 (Ty (ShOp (Ty DPR:$Vn),
2584 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2589 (Ty (ShOp (Ty DPR:$Vn),
2620 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2625 (ResTy (ShOp (ResTy QPR:$Vn),
2633 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2638 (ResTy (ShOp (ResTy QPR:$Vn),
2780 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2787 (Ty (ShOp (Ty DPR:$src1),
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 2663 ValueType Ty, SDNode ShOp>
2668 (Ty (ShOp (Ty DPR:$Vn),
2675 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2680 (Ty (ShOp (Ty DPR:$Vn),
2711 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2716 (ResTy (ShOp (ResTy QPR:$Vn),
2724 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2729 (ResTy (ShOp (ResTy QPR:$Vn),
2871 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2878 (Ty (ShOp (Ty DPR:$src1),
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1954 CreateShiftExtend(AArch64_AM::ShiftExtendType ShOp, unsigned Val, in CreateShiftExtend() argument
1957 Op->ShiftExtend.Type = ShOp; in CreateShiftExtend()
2659 AArch64_AM::ShiftExtendType ShOp = in tryParseOptionalShiftExtend() local
2676 if (ShOp == AArch64_AM::InvalidShiftExtend) in tryParseOptionalShiftExtend()
2685 if (ShOp == AArch64_AM::LSL || ShOp == AArch64_AM::LSR || in tryParseOptionalShiftExtend()
2686 ShOp == AArch64_AM::ASR || ShOp == AArch64_AM::ROR || in tryParseOptionalShiftExtend()
2687 ShOp == AArch64_AM::MSL) { in tryParseOptionalShiftExtend()
2696 AArch64Operand::CreateShiftExtend(ShOp, 0, false, S, E, getContext())); in tryParseOptionalShiftExtend()
2722 ShOp, MCE->getValue(), true, S, E, getContext())); in tryParseOptionalShiftExtend()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 2707 SDValue ShOp = N->getOperand(1); in WidenVecRes_POWI() local
2708 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp); in WidenVecRes_POWI()
2714 SDValue ShOp = N->getOperand(1); in WidenVecRes_Shift() local
2716 EVT ShVT = ShOp.getValueType(); in WidenVecRes_Shift()
2718 ShOp = GetWidenedVector(ShOp); in WidenVecRes_Shift()
2719 ShVT = ShOp.getValueType(); in WidenVecRes_Shift()
2725 ShOp = ModifyToType(ShOp, ShWidenVT); in WidenVecRes_Shift()
2727 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp); in WidenVecRes_Shift()
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| D | DAGCombiner.cpp | 3772 SDValue ShOp = N0->getOperand(1); in SimplifyBinOpWithSameOpcodeHands() local
3776 if (N->getOpcode() == ISD::XOR && !ShOp.isUndef()) { in SimplifyBinOpWithSameOpcodeHands()
3778 ShOp = DAG.getConstant(0, SDLoc(N), VT); in SimplifyBinOpWithSameOpcodeHands()
3780 ShOp = SDValue(); in SimplifyBinOpWithSameOpcodeHands()
3786 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) { in SimplifyBinOpWithSameOpcodeHands()
3790 return DAG.getVectorShuffle(VT, SDLoc(N), NewNode, ShOp, in SimplifyBinOpWithSameOpcodeHands()
3796 ShOp = N0->getOperand(0); in SimplifyBinOpWithSameOpcodeHands()
3797 if (N->getOpcode() == ISD::XOR && !ShOp.isUndef()) { in SimplifyBinOpWithSameOpcodeHands()
3799 ShOp = DAG.getConstant(0, SDLoc(N), VT); in SimplifyBinOpWithSameOpcodeHands()
3801 ShOp = SDValue(); in SimplifyBinOpWithSameOpcodeHands()
[all …]
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 2490 SDValue ShOp = N->getOperand(1); in WidenVecRes_POWI() local
2491 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp); in WidenVecRes_POWI()
2497 SDValue ShOp = N->getOperand(1); in WidenVecRes_Shift() local
2499 EVT ShVT = ShOp.getValueType(); in WidenVecRes_Shift()
2501 ShOp = GetWidenedVector(ShOp); in WidenVecRes_Shift()
2502 ShVT = ShOp.getValueType(); in WidenVecRes_Shift()
2508 ShOp = ModifyToType(ShOp, ShWidenVT); in WidenVecRes_Shift()
2510 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp); in WidenVecRes_Shift()
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| D | DAGCombiner.cpp | 2806 SDValue ShOp = N0->getOperand(1); in SimplifyBinOpWithSameOpcodeHands() local
2810 if (N->getOpcode() == ISD::XOR && !ShOp.isUndef()) { in SimplifyBinOpWithSameOpcodeHands()
2812 ShOp = DAG.getConstant(0, SDLoc(N), VT); in SimplifyBinOpWithSameOpcodeHands()
2814 ShOp = SDValue(); in SimplifyBinOpWithSameOpcodeHands()
2820 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) { in SimplifyBinOpWithSameOpcodeHands()
2824 return DAG.getVectorShuffle(VT, SDLoc(N), NewNode, ShOp, in SimplifyBinOpWithSameOpcodeHands()
2830 ShOp = N0->getOperand(0); in SimplifyBinOpWithSameOpcodeHands()
2831 if (N->getOpcode() == ISD::XOR && !ShOp.isUndef()) { in SimplifyBinOpWithSameOpcodeHands()
2833 ShOp = DAG.getConstant(0, SDLoc(N), VT); in SimplifyBinOpWithSameOpcodeHands()
2835 ShOp = SDValue(); in SimplifyBinOpWithSameOpcodeHands()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1449 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; in DecodeSORegMemOperand() local
1452 ShOp = ARM_AM::lsl; in DecodeSORegMemOperand()
1455 ShOp = ARM_AM::lsr; in DecodeSORegMemOperand()
1458 ShOp = ARM_AM::asr; in DecodeSORegMemOperand()
1461 ShOp = ARM_AM::ror; in DecodeSORegMemOperand()
1471 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); in DecodeSORegMemOperand()
1473 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); in DecodeSORegMemOperand()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1585 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; in DecodeSORegMemOperand() local
1588 ShOp = ARM_AM::lsl; in DecodeSORegMemOperand()
1591 ShOp = ARM_AM::lsr; in DecodeSORegMemOperand()
1594 ShOp = ARM_AM::asr; in DecodeSORegMemOperand()
1597 ShOp = ARM_AM::ror; in DecodeSORegMemOperand()
1601 if (ShOp == ARM_AM::ror && imm == 0) in DecodeSORegMemOperand()
1602 ShOp = ARM_AM::rrx; in DecodeSORegMemOperand()
1610 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); in DecodeSORegMemOperand()
1612 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); in DecodeSORegMemOperand()
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1586 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; in DecodeSORegMemOperand() local
1589 ShOp = ARM_AM::lsl; in DecodeSORegMemOperand()
1592 ShOp = ARM_AM::lsr; in DecodeSORegMemOperand()
1595 ShOp = ARM_AM::asr; in DecodeSORegMemOperand()
1598 ShOp = ARM_AM::ror; in DecodeSORegMemOperand()
1602 if (ShOp == ARM_AM::ror && imm == 0) in DecodeSORegMemOperand()
1603 ShOp = ARM_AM::rrx; in DecodeSORegMemOperand()
1611 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); in DecodeSORegMemOperand()
1613 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); in DecodeSORegMemOperand()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonPatterns.td | 1093 class OpshIRI_pat<InstHexagon MI, PatFrag Op, PatFrag ShOp,
1095 : Pat<(Op anyimm:$u8, (ShOp RegPred:$Rs, ImmPred:$U5)),
|