| /external/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineShifts.cpp | 543 BinaryOperator *ShiftOp = dyn_cast<BinaryOperator>(Op0); in FoldShiftByConstant() local
544 if (ShiftOp && !ShiftOp->isShift()) in FoldShiftByConstant()
545 ShiftOp = nullptr; in FoldShiftByConstant()
547 if (ShiftOp && isa<ConstantInt>(ShiftOp->getOperand(1))) { in FoldShiftByConstant()
561 ConstantInt *ShiftAmt1C = cast<ConstantInt>(ShiftOp->getOperand(1)); in FoldShiftByConstant()
566 Value *X = ShiftOp->getOperand(0); in FoldShiftByConstant()
571 if (I.getOpcode() == ShiftOp->getOpcode()) { in FoldShiftByConstant()
588 ShiftOp->getOpcode() == Instruction::Shl) { in FoldShiftByConstant()
600 ShiftOp->getOpcode() != Instruction::Shl && in FoldShiftByConstant()
601 ShiftOp->isExact()) { in FoldShiftByConstant()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Transforms/InstCombine/ |
| D | InstCombineShifts.cpp | 526 BinaryOperator *ShiftOp = dyn_cast<BinaryOperator>(Op0); in FoldShiftByConstant() local
527 if (ShiftOp && !ShiftOp->isShift()) in FoldShiftByConstant()
528 ShiftOp = 0; in FoldShiftByConstant()
530 if (ShiftOp && isa<ConstantInt>(ShiftOp->getOperand(1))) { in FoldShiftByConstant()
531 ConstantInt *ShiftAmt1C = cast<ConstantInt>(ShiftOp->getOperand(1)); in FoldShiftByConstant()
536 Value *X = ShiftOp->getOperand(0); in FoldShiftByConstant()
543 if (I.getOpcode() == ShiftOp->getOpcode()) { in FoldShiftByConstant()
559 ShiftOp->getOpcode() != Instruction::Shl) { in FoldShiftByConstant()
566 ShiftOp->getOpcode() == Instruction::Shl) { in FoldShiftByConstant()
576 ShiftOp->getOpcode() != Instruction::Shl) { in FoldShiftByConstant()
[all …]
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| /external/v8/src/arm/ |
| D | constants-arm.h | 236 enum ShiftOp { enum
575 inline int ShiftValue() const { return static_cast<ShiftOp>(Bits(6, 5)); } in ShiftValue()
576 inline ShiftOp ShiftField() const { in ShiftField()
577 return static_cast<ShiftOp>(BitField(6, 5)); in ShiftField()
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| D | assembler-arm.h | 410 explicit Operand(Register rm, ShiftOp shift_op, int shift_imm);
424 explicit Operand(Register rm, ShiftOp shift_op, Register rs);
480 ShiftOp shift_op() const { return shift_op_; } in shift_op()
486 ShiftOp shift_op_;
520 ShiftOp shift_op, int shift_imm, AddrMode am = Offset);
550 ShiftOp shift_op_;
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| D | disasm-arm.cc | 193 ShiftOp shift = instr->ShiftField(); in PrintShiftRm()
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| D | assembler-arm.cc | 375 Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) { in Operand()
396 Operand::Operand(Register rm, ShiftOp shift_op, Register rs) { in Operand()
433 MemOperand::MemOperand(Register rn, Register rm, ShiftOp shift_op, in MemOperand()
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| D | simulator-arm.cc | 1307 ShiftOp shift = instr->ShiftField(); in GetShiftRm()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstARM32.h | 114 Variable *Index, ShiftKind ShiftOp = kNoShift,
118 OperandARM32Mem(Func, Ty, Base, Index, ShiftOp, ShiftAmt, Mode);
123 ShiftKind getShiftOp() const { return ShiftOp; } in getShiftOp()
155 ShiftKind ShiftOp, uint16_t ShiftAmt, AddrMode Mode);
160 ShiftKind ShiftOp; variable
311 ShiftKind ShiftOp, Operand *ShiftAmt) { in create() argument
313 OperandARM32FlexReg(Func, Ty, Reg, ShiftOp, ShiftAmt); in create()
325 ShiftKind getShiftOp() const { return ShiftOp; } in getShiftOp()
330 OperandARM32FlexReg(Cfg *Func, Type Ty, Variable *Reg, ShiftKind ShiftOp,
334 ShiftKind ShiftOp; variable
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| D | IceInstARM32.cpp | 328 ShiftOp(kNoShift), ShiftAmt(0), Mode(Mode) { in OperandARM32Mem()
336 Variable *Index, ShiftKind ShiftOp, in OperandARM32Mem() argument
339 ShiftOp(ShiftOp), ShiftAmt(ShiftAmt), Mode(Mode) { in OperandARM32Mem()
476 ShiftKind ShiftOp, Operand *ShiftAmt) in OperandARM32FlexReg() argument
477 : OperandARM32Flex(kFlexReg, Ty), Reg(Reg), ShiftOp(ShiftOp), in OperandARM32FlexReg()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 566 unsigned ShiftOp = MI->getOperand(OpNum).getImm(); in printShiftImmOperand() local
567 bool isASR = (ShiftOp & (1 << 5)) != 0; in printShiftImmOperand()
568 unsigned Amt = ShiftOp & 0x1f; in printShiftImmOperand()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 713 unsigned ShiftOp = MI->getOperand(OpNum).getImm(); in printShiftImmOperand() local
714 bool isASR = (ShiftOp & (1 << 5)) != 0; in printShiftImmOperand()
715 unsigned Amt = ShiftOp & 0x1f; in printShiftImmOperand()
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 694 unsigned ShiftOp = MI->getOperand(OpNum).getImm(); in printShiftImmOperand() local
695 bool isASR = (ShiftOp & (1 << 5)) != 0; in printShiftImmOperand()
696 unsigned Amt = ShiftOp & 0x1f; in printShiftImmOperand()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMCodeEmitter.cpp | 1452 unsigned ShiftOp = MI.getOperand(3).getImm(); in emitSaturateInstruction() local
1453 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp); in emitSaturateInstruction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelDAGToDAG.cpp | 1785 unsigned ShiftOp = TrueOp->getSExtValue() == 1 ? ISD::SRL : ISD::SRA; in expandSelectBoolean() local
1786 Result = CurDAG->getNode(ShiftOp, DL, MVT::i32, Result, in expandSelectBoolean()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 2362 SDValue ShiftOp = N->getOperand(1); in ExpandIntRes_Shift() local
2367 if (ShiftOp.getValueType() != ShiftTy) in ExpandIntRes_Shift()
2368 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); in ExpandIntRes_Shift()
2370 SDValue Ops[] = { LHSL, LHSH, ShiftOp }; in ExpandIntRes_Shift()
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| D | SelectionDAGBuilder.cpp | 2201 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT); in visitBitTestCase() local
2210 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT), in visitBitTestCase()
2216 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT), in visitBitTestCase()
2221 DAG.getConstant(1, dl, VT), ShiftOp); in visitBitTestCase()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 2548 SDValue ShiftOp = N->getOperand(1); in ExpandIntRes_Shift() local
2553 if (ShiftOp.getValueType() != ShiftTy) in ExpandIntRes_Shift()
2554 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); in ExpandIntRes_Shift()
2556 SDValue Ops[] = { LHSL, LHSH, ShiftOp }; in ExpandIntRes_Shift()
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| D | DAGCombiner.cpp | 2006 SDValue ShiftOp = IsAdd ? N->getOperand(0) : N->getOperand(1); in foldAddSubOfSignBit() local
2008 if (!C || ShiftOp.getOpcode() != ISD::SRL) in foldAddSubOfSignBit()
2013 SDValue Not = ShiftOp.getOperand(0); in foldAddSubOfSignBit()
2019 EVT VT = ShiftOp.getValueType(); in foldAddSubOfSignBit()
2020 SDValue ShAmt = ShiftOp.getOperand(1); in foldAddSubOfSignBit()
5661 auto ShiftOp = dyn_cast<ConstantSDNode>(Op->getOperand(1)); in calculateByteProvider() local
5662 if (!ShiftOp) in calculateByteProvider()
5665 uint64_t BitShift = ShiftOp->getZExtValue(); in calculateByteProvider()
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| D | SelectionDAGBuilder.cpp | 2386 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT); in visitBitTestCase() local
2395 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT), in visitBitTestCase()
2401 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT), in visitBitTestCase()
2406 DAG.getConstant(1, dl, VT), ShiftOp); in visitBitTestCase()
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| /external/capstone/arch/ARM/ |
| D | ARMInstPrinter.c | 1324 unsigned ShiftOp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); in printShiftImmOperand() local
1325 bool isASR = (ShiftOp & (1 << 5)) != 0; in printShiftImmOperand()
1326 unsigned Amt = ShiftOp & 0x1f; in printShiftImmOperand()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 1742 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), in visitBitTestCase() local
1751 ShiftOp, in visitBitTestCase()
1758 ShiftOp, in visitBitTestCase()
1764 DAG.getConstant(1, VT), ShiftOp); in visitBitTestCase()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 3319 unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL; in emitINSERT_DF_VIDX() local
3364 BuildMI(*BB, MI, DL, TII->get(ShiftOp), LaneTmp1) in emitINSERT_DF_VIDX()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 3228 unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL; in emitINSERT_DF_VIDX() local
3273 BuildMI(*BB, MI, DL, TII->get(ShiftOp), LaneTmp1) in emitINSERT_DF_VIDX()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 28576 SDValue ShiftOp = Shift.getOperand(0); in foldXorTruncShiftIntoCmp() local
28577 EVT ShiftOpTy = ShiftOp.getValueType(); in foldXorTruncShiftIntoCmp()
28581 SDValue Cond = DAG.getSetCC(DL, SetCCResultType, ShiftOp, in foldXorTruncShiftIntoCmp()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 35259 SDValue ShiftOp = Shift.getOperand(0); in foldXorTruncShiftIntoCmp() local
35260 EVT ShiftOpTy = ShiftOp.getValueType(); in foldXorTruncShiftIntoCmp()
35264 SDValue Cond = DAG.getSetCC(DL, SetCCResultType, ShiftOp, in foldXorTruncShiftIntoCmp()
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