| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 354 unsigned ShiftReg; member
972 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
1507 unsigned ShiftReg, in CreateShiftedRegister() argument
1513 Op->RegShiftedReg.ShiftReg = ShiftReg; in CreateShiftedRegister()
1740 << ", " << RegShiftedReg.ShiftReg << ", " in print()
1890 int ShiftReg = 0; in tryParseShiftRegister() local
1895 ShiftReg = SrcReg; in tryParseShiftRegister()
1923 ShiftReg = tryParseRegister(); in tryParseShiftRegister()
1925 if (ShiftReg == -1) { in tryParseShiftRegister()
1936 if (ShiftReg && ShiftTy != ARM_AM::rrx) in tryParseShiftRegister()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 1085 unsigned ShiftReg = RI.createVirtualRegister(RC); in EmitShiftInstr() local
1105 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg) in EmitShiftInstr()
1112 .addReg(ShiftReg); in EmitShiftInstr()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 1231 unsigned ShiftReg = RI.createVirtualRegister(RC); in EmitShiftInstr() local
1251 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg) in EmitShiftInstr()
1258 .addReg(ShiftReg); in EmitShiftInstr()
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 4752 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary() local
4797 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) in EmitPartwordAtomicBinary()
4806 .addReg(incr).addReg(ShiftReg); in EmitPartwordAtomicBinary()
4814 .addReg(Mask2Reg).addReg(ShiftReg); in EmitPartwordAtomicBinary()
4839 .addReg(ShiftReg); in EmitPartwordAtomicBinary()
5074 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); in EmitInstrWithCustomInserter() local
5129 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) in EmitInstrWithCustomInserter()
5138 .addReg(newval).addReg(ShiftReg); in EmitInstrWithCustomInserter()
5140 .addReg(oldval).addReg(ShiftReg); in EmitInstrWithCustomInserter()
5149 .addReg(Mask2Reg).addReg(ShiftReg); in EmitInstrWithCustomInserter()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 1453 unsigned ShiftReg = RI.createVirtualRegister(RC); in EmitShiftInstr() local
1473 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg) in EmitShiftInstr()
1480 .addReg(ShiftReg); in EmitShiftInstr()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.cpp | 1511 unsigned ShiftReg = RI.createVirtualRegister(RC); in insertShift() local
1528 BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftReg) in insertShift()
1538 BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg); in insertShift()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 771 unsigned ShiftReg; member
1190 RegShiftedReg.ShiftReg); in isRegShiftedReg()
2059 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
2966 unsigned ShiftReg, unsigned ShiftImm, SMLoc S, in CreateShiftedRegister() argument
2971 Op->RegShiftedReg.ShiftReg = ShiftReg; in CreateShiftedRegister()
3282 << " " << RegShiftedReg.ShiftReg << ">"; in print()
3450 int ShiftReg = 0; in tryParseShiftRegister() local
3455 ShiftReg = SrcReg; in tryParseShiftRegister()
3490 ShiftReg = tryParseRegister(); in tryParseShiftRegister()
3491 if (ShiftReg == -1) { in tryParseShiftRegister()
[all …]
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 537 unsigned ShiftReg; member
1806 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
2650 unsigned ShiftReg, unsigned ShiftImm, SMLoc S, in CreateShiftedRegister() argument
2655 Op->RegShiftedReg.ShiftReg = ShiftReg; in CreateShiftedRegister()
2954 << " " << RegShiftedReg.ShiftReg << ">"; in print()
3123 int ShiftReg = 0; in tryParseShiftRegister() local
3128 ShiftReg = SrcReg; in tryParseShiftRegister()
3163 ShiftReg = tryParseRegister(); in tryParseShiftRegister()
3164 if (ShiftReg == -1) { in tryParseShiftRegister()
3175 if (ShiftReg && ShiftTy != ARM_AM::rrx) in tryParseShiftRegister()
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 8543 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary() local
8588 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) in EmitPartwordAtomicBinary()
8597 .addReg(incr).addReg(ShiftReg); in EmitPartwordAtomicBinary()
8605 .addReg(Mask2Reg).addReg(ShiftReg); in EmitPartwordAtomicBinary()
8630 .addReg(ShiftReg); in EmitPartwordAtomicBinary()
9258 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); in EmitInstrWithCustomInserter() local
9313 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) in EmitInstrWithCustomInserter()
9322 .addReg(newval).addReg(ShiftReg); in EmitInstrWithCustomInserter()
9324 .addReg(oldval).addReg(ShiftReg); in EmitInstrWithCustomInserter()
9333 .addReg(Mask2Reg).addReg(ShiftReg); in EmitInstrWithCustomInserter()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 3680 unsigned ShiftReg = emitLSR_ri(MVT::i64, MVT::i64, MulReg, in fastLowerIntrinsicCall() local
3684 ShiftReg = fastEmitInst_extractsubreg(VT, ShiftReg, /*IsKill=*/true, in fastLowerIntrinsicCall()
3686 emitSubs_rs(VT, ShiftReg, /*IsKill=*/true, MulReg, /*IsKill=*/false, in fastLowerIntrinsicCall()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 3594 unsigned ShiftReg = emitLSR_ri(MVT::i64, MVT::i64, MulReg, in fastLowerIntrinsicCall() local
3598 ShiftReg = fastEmitInst_extractsubreg(VT, ShiftReg, /*IsKill=*/true, in fastLowerIntrinsicCall()
3600 emitSubs_rs(VT, ShiftReg, /*IsKill=*/true, MulReg, /*IsKill=*/false, in fastLowerIntrinsicCall()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 9839 unsigned ShiftReg = in EmitPartwordAtomicBinary() local
9886 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) in EmitPartwordAtomicBinary()
9895 .addReg(incr).addReg(ShiftReg); in EmitPartwordAtomicBinary()
9903 .addReg(Mask2Reg).addReg(ShiftReg); in EmitPartwordAtomicBinary()
9926 .addReg(SReg).addReg(ShiftReg); in EmitPartwordAtomicBinary()
9954 .addReg(ShiftReg); in EmitPartwordAtomicBinary()
10626 unsigned ShiftReg = in EmitInstrWithCustomInserter() local
10683 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg) in EmitInstrWithCustomInserter()
10692 .addReg(newval).addReg(ShiftReg); in EmitInstrWithCustomInserter()
10694 .addReg(oldval).addReg(ShiftReg); in EmitInstrWithCustomInserter()
[all …]
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