Searched refs:Src0SubRC (Results 1 – 2 of 2) sorted by relevance
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 2713 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitUnaryOp() local
2716 AMDGPU::sub0, Src0SubRC); in splitScalar64BitUnaryOp()
2727 AMDGPU::sub1, Src0SubRC); in splitScalar64BitUnaryOp()
2767 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitBinaryOp() local
2775 AMDGPU::sub0, Src0SubRC); in splitScalar64BitBinaryOp()
2789 AMDGPU::sub1, Src0SubRC); in splitScalar64BitBinaryOp()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 4193 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitUnaryOp() local
4196 AMDGPU::sub0, Src0SubRC); in splitScalar64BitUnaryOp()
4206 AMDGPU::sub1, Src0SubRC); in splitScalar64BitUnaryOp()
4249 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitAddSub() local
4253 AMDGPU::sub0, Src0SubRC); in splitScalar64BitAddSub()
4259 AMDGPU::sub1, Src0SubRC); in splitScalar64BitAddSub()
4313 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitBinaryOp() local
4321 AMDGPU::sub0, Src0SubRC); in splitScalar64BitBinaryOp()
4335 AMDGPU::sub1, Src0SubRC); in splitScalar64BitBinaryOp()
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