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Searched refs:Src1RC (Results 1 – 6 of 6) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.td1242 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
1244 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1249 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
1275 Src1Mod:$src1_modifiers, Src1RC:$src1,
1278 Src1Mod:$src1_modifiers, Src1RC:$src1,
1283 (ins Src0RC:$src0, Src1RC:$src1, clampmod:$clamp),
1284 (ins Src0RC:$src0, Src1RC:$src1))
1292 Src1Mod:$src1_modifiers, Src1RC:$src1,
1296 Src1Mod:$src1_modifiers, Src1RC:$src1,
1302 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2, clampmod:$clamp),
[all …]
DSIFixSGPRCopies.cpp696 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC; in runOnMachineFunction() local
699 Src1RC = MRI.getRegClass(MI.getOperand(2).getReg()); in runOnMachineFunction()
701 (TRI->hasVGPRs(Src0RC) || TRI->hasVGPRs(Src1RC))) { in runOnMachineFunction()
DSIInstrInfo.cpp4248 const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg()); in splitScalar64BitAddSub() local
4250 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); in splitScalar64BitAddSub()
4254 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, in splitScalar64BitAddSub()
4260 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, in splitScalar64BitAddSub()
4314 const TargetRegisterClass *Src1RC = Src1.isReg() ? in splitScalar64BitBinaryOp() local
4318 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
4322 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, in splitScalar64BitBinaryOp()
4336 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, in splitScalar64BitBinaryOp()
/external/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp356 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC; in runOnMachineFunction() local
359 Src1RC = MRI.getRegClass(MI.getOperand(2).getReg()); in runOnMachineFunction()
361 (TRI->hasVGPRs(Src0RC) || TRI->hasVGPRs(Src1RC))) { in runOnMachineFunction()
DSIInstrInfo.td1189 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
1191 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1196 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
1218 FPInputMods:$src1_modifiers, Src1RC:$src1,
1222 (ins Src0RC:$src0, Src1RC:$src1)
1228 FPInputMods:$src1_modifiers, Src1RC:$src1,
1233 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
1237 class getInsDPP <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs,
1259 FPInputMods:$src1_modifiers, Src1RC:$src1,
1264 (ins Src0RC:$src0, Src1RC:$src1, dpp_ctrl:$dpp_ctrl,
[all …]
DSIInstrInfo.cpp2768 const TargetRegisterClass *Src1RC = Src1.isReg() ? in splitScalar64BitBinaryOp() local
2772 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
2776 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, in splitScalar64BitBinaryOp()
2790 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, in splitScalar64BitBinaryOp()