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Searched refs:SrcIdx (Results 1 – 25 of 35) sorted by relevance

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/external/llvm/lib/CodeGen/
DRegisterCoalescer.h42 unsigned SrcIdx; variable
61 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0), in CoalescerPair()
68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0), in CoalescerPair()
109 unsigned getSrcIdx() const { return SrcIdx; } in getSrcIdx()
DTwoAddressInstructionPass.cpp132 unsigned SrcIdx, unsigned DstIdx,
1211 unsigned SrcIdx, unsigned DstIdx, in tryInstructionTransform() argument
1218 unsigned regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform()
1227 bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist); in tryInstructionTransform()
1253 regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform()
1408 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) { in collectTiedOperands() local
1410 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx)) in collectTiedOperands()
1413 MachineOperand &SrcMO = MI->getOperand(SrcIdx); in collectTiedOperands()
1427 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx, in collectTiedOperands()
1435 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx)); in collectTiedOperands()
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DRegisterCoalescer.cpp315 SrcIdx = DstIdx = 0; in setRegisters()
362 SrcIdx, DstIdx); in setRegisters()
367 SrcIdx = DstSub; in setRegisters()
384 if (DstIdx && !SrcIdx) { in setRegisters()
386 std::swap(SrcIdx, DstIdx); in setRegisters()
405 std::swap(SrcIdx, DstIdx); in flip()
429 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state."); in isCoalescable()
443 return TRI.composeSubRegIndices(SrcIdx, SrcSub) == in isCoalescable()
885 unsigned SrcIdx = CP.isFlipped() ? CP.getDstIdx() : CP.getSrcIdx(); in reMaterializeTrivialDef() local
927 if (SrcIdx && DstIdx) in reMaterializeTrivialDef()
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DTargetRegisterInfo.cpp299 unsigned SrcIdx, DefIdx; in shareSameRegisterFile() local
302 SrcIdx, DefIdx) != nullptr; in shareSameRegisterFile()
DPeepholeOptimizer.cpp1696 unsigned SrcIdx = Def->getNumOperands(); in getNextSourceFromBitcast() local
1697 for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx; in getNextSourceFromBitcast()
1706 if (SrcIdx != EndOpIdx) in getNextSourceFromBitcast()
1709 SrcIdx = OpIdx; in getNextSourceFromBitcast()
1711 const MachineOperand &Src = Def->getOperand(SrcIdx); in getNextSourceFromBitcast()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DTwoAddressInstructionPass.cpp126 unsigned SrcIdx, unsigned DstIdx,
864 unsigned SrcIdx, unsigned DstIdx, unsigned Dist, in TryInstructionTransform() argument
868 unsigned regB = mi->getOperand(SrcIdx).getReg(); in TryInstructionTransform()
890 if (SrcIdx == SrcOp1) in TryInstructionTransform()
892 else if (SrcIdx == SrcOp2) in TryInstructionTransform()
1093 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) { in runOnMachineFunction() local
1095 if (!mi->isRegTiedToDefOperand(SrcIdx, &DstIdx)) in runOnMachineFunction()
1104 assert(mi->getOperand(SrcIdx).isReg() && in runOnMachineFunction()
1105 mi->getOperand(SrcIdx).getReg() && in runOnMachineFunction()
1106 mi->getOperand(SrcIdx).isUse() && in runOnMachineFunction()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DTwoAddressInstructionPass.cpp157 unsigned SrcIdx, unsigned DstIdx,
1266 unsigned SrcIdx, unsigned DstIdx, in tryInstructionTransform() argument
1273 unsigned regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform()
1282 bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist); in tryInstructionTransform()
1308 regB = MI.getOperand(SrcIdx).getReg(); in tryInstructionTransform()
1463 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) { in collectTiedOperands() local
1465 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx)) in collectTiedOperands()
1468 MachineOperand &SrcMO = MI->getOperand(SrcIdx); in collectTiedOperands()
1482 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx, in collectTiedOperands()
1490 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx)); in collectTiedOperands()
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DRegisterCoalescer.h41 unsigned SrcIdx = 0; variable
105 unsigned getSrcIdx() const { return SrcIdx; } in getSrcIdx()
DRegisterCoalescer.cpp349 SrcIdx = DstIdx = 0; in setRegisters()
396 SrcIdx, DstIdx); in setRegisters()
401 SrcIdx = DstSub; in setRegisters()
418 if (DstIdx && !SrcIdx) { in setRegisters()
420 std::swap(SrcIdx, DstIdx); in setRegisters()
439 std::swap(SrcIdx, DstIdx); in flip()
463 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state."); in isCoalescable()
477 return TRI.composeSubRegIndices(SrcIdx, SrcSub) == in isCoalescable()
1101 unsigned SrcIdx = CP.isFlipped() ? CP.getDstIdx() : CP.getSrcIdx(); in reMaterializeTrivialDef() local
1143 if (SrcIdx && DstIdx) in reMaterializeTrivialDef()
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DTargetRegisterInfo.cpp360 unsigned SrcIdx, DefIdx; in shareSameRegisterFile() local
363 SrcIdx, DefIdx) != nullptr; in shareSameRegisterFile()
DPeepholeOptimizer.cpp1841 unsigned SrcIdx = Def->getNumOperands(); in getNextSourceFromBitcast() local
1842 for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx; in getNextSourceFromBitcast()
1851 if (SrcIdx != EndOpIdx) in getNextSourceFromBitcast()
1854 SrcIdx = OpIdx; in getNextSourceFromBitcast()
1864 const MachineOperand &Src = Def->getOperand(SrcIdx); in getNextSourceFromBitcast()
/external/swiftshader/third_party/LLVM/lib/Transforms/InstCombine/
DInstCombineVectorOps.cpp215 int SrcIdx = getShuffleMask(SVI)[Elt->getZExtValue()]; in visitExtractElementInst() local
220 if (SrcIdx < 0) in visitExtractElementInst()
222 if (SrcIdx < (int)LHSWidth) in visitExtractElementInst()
225 SrcIdx -= LHSWidth; in visitExtractElementInst()
231 SrcIdx, false)); in visitExtractElementInst()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86MCInstLower.cpp1879 unsigned SrcIdx, MaskIdx; in EmitInstruction() local
1888 SrcIdx = 1; MaskIdx = 5; break; in EmitInstruction()
1892 SrcIdx = 2; MaskIdx = 6; break; in EmitInstruction()
1896 SrcIdx = 3; MaskIdx = 7; break; in EmitInstruction()
1907 OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask), in EmitInstruction()
1937 unsigned SrcIdx, MaskIdx; in EmitInstruction() local
1946 SrcIdx = 1; MaskIdx = 5; ElSize = 32; break; in EmitInstruction()
1950 SrcIdx = 2; MaskIdx = 6; ElSize = 32; break; in EmitInstruction()
1954 SrcIdx = 3; MaskIdx = 7; ElSize = 32; break; in EmitInstruction()
1960 SrcIdx = 1; MaskIdx = 5; ElSize = 64; break; in EmitInstruction()
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/external/llvm/lib/Target/AMDGPU/
DR600InstrInfo.h108 int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
312 MachineOperand &getFlagOp(MachineInstr &MI, unsigned SrcIdx = 0,
DR600InstrInfo.cpp262 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const { in getSelIdx()
278 if (getOperandIdx(Opcode, Row[0]) == (int)SrcIdx) { in getSelIdx()
323 int SrcIdx = getOperandIdx(MI.getOpcode(), OpTable[j][0]); in getSrcs() local
324 if (SrcIdx < 0) in getSrcs()
326 MachineOperand &MO = MI.getOperand(SrcIdx); in getSrcs()
1427 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr &MI, unsigned SrcIdx, in getFlagOp() argument
1449 switch (SrcIdx) { in getFlagOp()
1466 switch (SrcIdx) { in getFlagOp()
DR600ISelLowering.h94 bool FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DR600InstrInfo.h113 int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
311 MachineOperand &getFlagOp(MachineInstr &MI, unsigned SrcIdx = 0,
DR600InstrInfo.cpp256 int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const { in getSelIdx()
272 if (getOperandIdx(Opcode, Row[0]) == (int)SrcIdx) { in getSelIdx()
317 int SrcIdx = getOperandIdx(MI.getOpcode(), OpTable[j][0]); in getSrcs() local
318 if (SrcIdx < 0) in getSrcs()
320 MachineOperand &MO = MI.getOperand(SrcIdx); in getSrcs()
1402 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr &MI, unsigned SrcIdx, in getFlagOp() argument
1424 switch (SrcIdx) { in getFlagOp()
1441 switch (SrcIdx) { in getFlagOp()
DR600ISelLowering.h101 bool FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Scalar/
DInferAddressSpaces.cpp956 int SrcIdx = U.getOperandNo(); in rewriteWithNewAddressSpaces() local
957 int OtherIdx = (SrcIdx == 0) ? 1 : 0; in rewriteWithNewAddressSpaces()
963 Cmp->setOperand(SrcIdx, NewV); in rewriteWithNewAddressSpaces()
971 Cmp->setOperand(SrcIdx, NewV); in rewriteWithNewAddressSpaces()
/external/llvm/lib/Transforms/InstCombine/
DInstCombineVectorOps.cpp229 int SrcIdx = SVI->getMaskValue(Elt->getZExtValue()); in visitExtractElementInst() local
234 if (SrcIdx < 0) in visitExtractElementInst()
236 if (SrcIdx < (int)LHSWidth) in visitExtractElementInst()
239 SrcIdx -= LHSWidth; in visitExtractElementInst()
245 SrcIdx, false)); in visitExtractElementInst()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/InstCombine/
DInstCombineVectorOps.cpp255 int SrcIdx = SVI->getMaskValue(Elt->getZExtValue()); in visitExtractElementInst() local
260 if (SrcIdx < 0) in visitExtractElementInst()
262 if (SrcIdx < (int)LHSWidth) in visitExtractElementInst()
265 SrcIdx -= LHSWidth; in visitExtractElementInst()
271 SrcIdx, false)); in visitExtractElementInst()
DInstCombineSimplifyDemanded.cpp949 for (unsigned SrcIdx = 0; SrcIdx < 4; ++SrcIdx) { in simplifyAMDGCNMemoryIntrinsicDemanded() local
950 const unsigned Bit = 1 << SrcIdx; in simplifyAMDGCNMemoryIntrinsicDemanded()
/external/llvm/lib/Target/X86/
DX86MCInstLower.cpp1444 unsigned SrcIdx, MaskIdx; in EmitInstruction() local
1453 SrcIdx = 1; MaskIdx = 5; break; in EmitInstruction()
1457 SrcIdx = 2; MaskIdx = 6; break; in EmitInstruction()
1461 SrcIdx = 3; MaskIdx = 7; break; in EmitInstruction()
1467 const MachineOperand &SrcOp = MI->getOperand(SrcIdx); in EmitInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/AsmParser/
DAMDGPUAsmParser.cpp2350 for (int SrcIdx : SrcIndices) { in validateEarlyClobberLimitations() local
2351 if (SrcIdx == -1) break; in validateEarlyClobberLimitations()
2352 const MCOperand &Src = Inst.getOperand(SrcIdx); in validateEarlyClobberLimitations()
3593 int SrcIdx = 0; in cvtExp() local
3600 assert(SrcIdx < 4); in cvtExp()
3601 OperandIdx[SrcIdx] = Inst.size(); in cvtExp()
3603 ++SrcIdx; in cvtExp()
3608 assert(SrcIdx < 4); in cvtExp()
3609 OperandIdx[SrcIdx] = Inst.size(); in cvtExp()
3611 ++SrcIdx; in cvtExp()
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