Searched refs:SrcOp2 (Results 1 – 7 of 7) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | AsmMatcherEmitter.cpp | 1829 unsigned SrcOp2 = 0; in buildAliasResultOperands() local
1840 SrcOp2 = findAsmOperandNamed(Name, Insert.first->second); in buildAliasResultOperands()
1845 Insert.first->second = SrcOp2; in buildAliasResultOperands()
1849 SrcOp2 = (SrcOp2 == (unsigned)-1) ? SrcOp1 : SrcOp2; in buildAliasResultOperands()
1861 SrcOp2 = findAsmOperand(Name, SubIdx); in buildAliasResultOperands()
1863 ResOperand::getTiedOp((unsigned)-1, SrcOp1, SrcOp2)); in buildAliasResultOperands()
1865 ResOperands.push_back(ResOperand::getTiedOp(TiedOp, SrcOp1, SrcOp2)); in buildAliasResultOperands()
2158 uint8_t SrcOp2 = in emitConvertFuncs() local
2163 utostr(SrcOp1) + '_' + utostr(SrcOp2); in emitConvertFuncs()
2168 ConversionRow.push_back(SrcOp2); in emitConvertFuncs()
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 1157 const MachineOperand &SrcOp2, in getShuffleComment() argument
1175 SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem"; in getShuffleComment()
1533 const MachineOperand &SrcOp2 = MI->getOperand(2); in EmitInstruction() local
1551 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp1, SrcOp2, Mask)); in EmitInstruction()
1563 const MachineOperand &SrcOp2 = MI->getOperand(2); in EmitInstruction() local
1570 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp1, SrcOp2, Mask)); in EmitInstruction()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | TwoAddressInstructionPass.cpp | 883 unsigned SrcOp1, SrcOp2; in TryInstructionTransform() local
889 TII->findCommutedOpIndices(mi, SrcOp1, SrcOp2)) { in TryInstructionTransform()
891 regCIdx = SrcOp2; in TryInstructionTransform()
892 else if (SrcIdx == SrcOp2) in TryInstructionTransform()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 1448 const MachineOperand &SrcOp2 = MI->getOperand(SrcOp2Idx); in getShuffleComment() local
1454 SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem"; in getShuffleComment()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenAsmMatcher.inc | 4815 auto &SrcOp2 = Operands[OpndNum2];
4816 if (SrcOp1->isReg() && SrcOp2->isReg()) {
4817 if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) {
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 11803 auto &SrcOp2 = Operands[OpndNum2];
11804 if (SrcOp1->isReg() && SrcOp2->isReg()) {
11805 if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) {
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
| D | X86GenAsmMatcher.inc | 6501 auto &SrcOp2 = Operands[OpndNum2];
6502 if (SrcOp1->isReg() && SrcOp2->isReg()) {
6503 if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) {
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