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Searched refs:SrcRC (Results 1 – 25 of 76) sorted by relevance

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/external/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp135 const TargetRegisterClass *SrcRC = in getCopyRegClasses() local
148 return std::make_pair(SrcRC, DstRC); in getCopyRegClasses()
151 static bool isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC, in isVGPRToSGPRCopy() argument
154 return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC); in isVGPRToSGPRCopy()
157 static bool isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC, in isSGPRToVGPRCopy() argument
160 return TRI.isSGPRClass(SrcRC) && TRI.hasVGPRs(DstRC); in isSGPRToVGPRCopy()
193 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence() local
194 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI); in foldVGPRCopyIntoRegSequence()
196 if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) in foldVGPRCopyIntoRegSequence()
220 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in foldVGPRCopyIntoRegSequence() local
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DSILowerI1Copies.cpp103 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src.getReg()); in runOnMachineFunction() local
106 TRI->getCommonSubClass(SrcRC, &AMDGPU::SGPR_64RegClass)) { in runOnMachineFunction()
133 SrcRC == &AMDGPU::VReg_1RegClass) { in runOnMachineFunction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp167 const TargetRegisterClass *SrcRC = in getCopyRegClasses() local
180 return std::make_pair(SrcRC, DstRC); in getCopyRegClasses()
183 static bool isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC, in isVGPRToSGPRCopy() argument
186 return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC); in isVGPRToSGPRCopy()
189 static bool isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC, in isSGPRToVGPRCopy() argument
192 return TRI.isSGPRClass(SrcRC) && TRI.hasVGPRs(DstRC); in isSGPRToVGPRCopy()
254 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence() local
255 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI); in foldVGPRCopyIntoRegSequence()
257 if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) in foldVGPRCopyIntoRegSequence()
284 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in foldVGPRCopyIntoRegSequence() local
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DSILowerI1Copies.cpp103 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src.getReg()); in runOnMachineFunction() local
108 TRI->getCommonSubClass(SrcRC, &AMDGPU::SGPR_64RegClass)) { in runOnMachineFunction()
136 SrcRC == &AMDGPU::VReg_1RegClass) { in runOnMachineFunction()
DSIRegisterInfo.h169 const TargetRegisterClass *SrcRC,
210 const TargetRegisterClass *SrcRC,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.cpp39 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in copyPhysReg() local
41 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC)) in copyPhysReg()
50 Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr in copyPhysReg()
53 Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr in copyPhysReg()
56 Op = (SrcRC == &NVPTX::Float16RegsRegClass ? NVPTX::FMOV16rr in copyPhysReg()
61 Op = (SrcRC == &NVPTX::Float32RegsRegClass ? NVPTX::FMOV32rr in copyPhysReg()
64 Op = (SrcRC == &NVPTX::Float64RegsRegClass ? NVPTX::FMOV64rr in copyPhysReg()
/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.cpp39 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in copyPhysReg() local
41 if (DestRC->getSize() != SrcRC->getSize()) in copyPhysReg()
50 Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr in copyPhysReg()
53 Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr in copyPhysReg()
56 Op = (SrcRC == &NVPTX::Float32RegsRegClass ? NVPTX::FMOV32rr in copyPhysReg()
59 Op = (SrcRC == &NVPTX::Float64RegsRegClass ? NVPTX::FMOV64rr in copyPhysReg()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstructionSelector.cpp111 const TargetRegisterClass *SrcRC) const;
247 const TargetRegisterClass *SrcRC = in selectCopy() local
251 if (SrcRC != DstRC) { in selectCopy()
259 .addImm(getSubRegIndex(SrcRC)); in selectCopy()
285 const TargetRegisterClass *SrcRC = getRegClassFromGRPhysReg(SrcReg); in selectCopy() local
287 if (DstRC != SrcRC) { in selectCopy()
665 const TargetRegisterClass *SrcRC) { in canTurnIntoCOPY() argument
668 (SrcRC == &X86::VR128RegClass || SrcRC == &X86::VR128XRegClass); in canTurnIntoCOPY()
674 const TargetRegisterClass *SrcRC) const { in selectTurnIntoCOPY()
676 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || in selectTurnIntoCOPY()
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DX86DomainReassignment.cpp71 static const TargetRegisterClass *getDstRC(const TargetRegisterClass *SrcRC, in getDstRC() argument
74 if (X86::GR8RegClass.hasSubClassEq(SrcRC)) in getDstRC()
76 if (X86::GR16RegClass.hasSubClassEq(SrcRC)) in getDstRC()
78 if (X86::GR32RegClass.hasSubClassEq(SrcRC)) in getDstRC()
80 if (X86::GR64RegClass.hasSubClassEq(SrcRC)) in getDstRC()
/external/llvm/lib/CodeGen/
DTargetRegisterInfo.cpp292 const TargetRegisterClass *SrcRC, in shareSameRegisterFile() argument
295 if (DefRC == SrcRC) in shareSameRegisterFile()
301 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, in shareSameRegisterFile()
309 std::swap(DefRC, SrcRC); in shareSameRegisterFile()
314 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr; in shareSameRegisterFile()
317 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; in shareSameRegisterFile()
322 const TargetRegisterClass *SrcRC, in shouldRewriteCopySrc() argument
325 return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg); in shouldRewriteCopySrc()
DDetectDeadLanes.cpp161 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in isCrossCopy() local
162 if (DstRC == SrcRC) in isCrossCopy()
187 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA, in isCrossCopy()
190 return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx); in isCrossCopy()
192 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx); in isCrossCopy()
193 return !TRI.getCommonSubClass(SrcRC, DstRC); in isCrossCopy()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DTargetRegisterInfo.cpp353 const TargetRegisterClass *SrcRC, in shareSameRegisterFile() argument
356 if (DefRC == SrcRC) in shareSameRegisterFile()
362 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, in shareSameRegisterFile()
370 std::swap(DefRC, SrcRC); in shareSameRegisterFile()
375 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr; in shareSameRegisterFile()
378 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; in shareSameRegisterFile()
383 const TargetRegisterClass *SrcRC, in shouldRewriteCopySrc() argument
386 return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg); in shouldRewriteCopySrc()
DDetectDeadLanes.cpp159 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in isCrossCopy() local
160 if (DstRC == SrcRC) in isCrossCopy()
185 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA, in isCrossCopy()
188 return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx); in isCrossCopy()
190 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx); in isCrossCopy()
191 return !TRI.getCommonSubClass(SrcRC, DstRC); in isCrossCopy()
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsInstrFormats.td273 RegisterClass DstRC, RegisterClass SrcRC> :
274 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
281 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode> :
282 FFR<0x11, funct, fmt, (outs DstRC:$fd), (ins SrcRC:$fs),
284 [(set DstRC:$fd, (OpNode SrcRC:$fs))]> {
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCVSXCopy.cpp104 const TargetRegisterClass *SrcRC = &PPC::VSLRCRegClass; in processBlock() local
110 unsigned NewVReg = MRI.createVirtualRegister(SrcRC); in processBlock()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMicroMips32r6InstrInfo.td655 RegisterOperand SrcRC, InstrItinClass Itin> {
656 dag InOperandList = (ins SrcRC:$rt, uimm3:$sel);
665 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
668 dag InOperandList = (ins SrcRC:$rt);
671 list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))];
677 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
679 dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt);
691 RegisterOperand SrcRC, InstrItinClass Itin> {
692 dag InOperandList = (ins SrcRC:$rt);
713 RegisterOperand SrcRC, InstrItinClass Itin> {
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DMipsInstrFPU.td126 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
128 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
129 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
149 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
151 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
152 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT {
156 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
158 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
159 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>, HARDFLOAT {
163 class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
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/external/llvm/lib/Target/Mips/
DMicroMips32r6InstrInfo.td669 RegisterOperand SrcRC> {
670 dag InOperandList = (ins SrcRC:$rt, uimm3:$sel);
678 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
681 dag InOperandList = (ins SrcRC:$rt);
684 list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))];
690 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
692 dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt);
704 RegisterOperand SrcRC> {
705 dag InOperandList = (ins SrcRC:$rt);
725 RegisterOperand SrcRC> {
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DMipsInstrFPU.td121 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
123 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
144 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
146 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
147 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT;
149 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
151 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
152 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>, HARDFLOAT;
154 class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
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/external/llvm/lib/Target/PowerPC/
DPPCVSXCopy.cpp106 const TargetRegisterClass *SrcRC = in processBlock() local
115 unsigned NewVReg = MRI.createVirtualRegister(SrcRC); in processBlock()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/
DInstructionSelect.cpp171 auto SrcRC = MRI.getRegClass(SrcReg); in runOnMachineFunction() local
173 if (SrcRC == DstRC) { in runOnMachineFunction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64InstructionSelector.cpp353 const TargetRegisterClass *SrcRC = getRegClassForTypeOnBank( in selectCopy() local
355 if (SrcRC == &AArch64::GPR32allRegClass) in selectCopy()
392 const TargetRegisterClass *SrcRC = in selectCopy() local
395 if (!SrcRC) { in selectCopy()
397 SrcRC = getRegClassForTypeOnBank(MRI.getType(SrcReg), *RB, RBI, true); in selectCopy()
400 if (RC == &AArch64::GPR32allRegClass && SrcRC == &AArch64::FPR16RegClass) { in selectCopy()
411 SrcRC == &AArch64::GPR32allRegClass) { in selectCopy()
1170 const TargetRegisterClass *SrcRC = in select() local
1172 if (!SrcRC) in select()
1175 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || in select()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.cpp248 const TargetRegisterClass *SrcRC, in shouldCoalesce() argument
258 (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64))) in shouldCoalesce()
265 unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0); in shouldCoalesce()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DRegisterCoalescer.cpp156 const TargetRegisterClass *SrcRC,
289 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); in setRegisters() local
291 if (!TRI.getCommonSubClass(DstRC, SrcRC)) in setRegisters()
306 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); in setRegisters() local
309 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); in setRegisters()
311 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); in setRegisters()
314 CrossClass = NewRC != DstRC || NewRC != SrcRC; in setRegisters()
1103 const TargetRegisterClass *SrcRC, in isWinToJoinCrossClass() argument
1135 if (SrcRC != NewRC && SrcSize > ThresSize) { in isWinToJoinCrossClass()
1136 unsigned SrcRCCount = RegClassInfo.getNumAllocatableRegs(SrcRC); in isWinToJoinCrossClass()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrMMX.td104 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
107 def irr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
108 [(set DstRC:$dst, (Int SrcRC:$src))], d>;
113 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
116 def irr : PI<opc, MRMSrcReg, (outs DstRC:$dst),(ins DstRC:$src1, SrcRC:$src2),
117 asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>;

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