Searched refs:SrcReg0 (Results 1 – 5 of 5) sorted by relevance
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
D | AArch64SIMDInstrOpt.cpp | 431 unsigned SrcReg0 = MI.getOperand(1).getReg(); in optimizeVectElement() local 452 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement() 464 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
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D | AArch64InstrInfo.cpp | 4045 unsigned SrcReg0 = MUL->getOperand(1).getReg(); in genFusedMultiply() local 4063 if (TargetRegisterInfo::isVirtualRegister(SrcReg0)) in genFusedMultiply() 4064 MRI.constrainRegClass(SrcReg0, RC); in genFusedMultiply() 4073 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply() 4079 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply() 4085 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply() 4122 unsigned SrcReg0 = MUL->getOperand(1).getReg(); in genMaddR() local 4129 if (TargetRegisterInfo::isVirtualRegister(SrcReg0)) in genMaddR() 4130 MRI.constrainRegClass(SrcReg0, RC); in genMaddR() 4138 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genMaddR()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64InstrInfo.cpp | 3290 unsigned SrcReg0 = MUL->getOperand(1).getReg(); in genFusedMultiply() local 3299 if (TargetRegisterInfo::isVirtualRegister(SrcReg0)) in genFusedMultiply() 3300 MRI.constrainRegClass(SrcReg0, RC); in genFusedMultiply() 3309 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply() 3315 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply() 3321 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply() 3354 unsigned SrcReg0 = MUL->getOperand(1).getReg(); in genMaddR() local 3361 if (TargetRegisterInfo::isVirtualRegister(SrcReg0)) in genMaddR() 3362 MRI.constrainRegClass(SrcReg0, RC); in genMaddR() 3370 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genMaddR()
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/external/mesa3d/src/gallium/drivers/r300/compiler/ |
D | radeon_program_alu.c | 63 struct rc_src_register SrcReg0, struct rc_src_register SrcReg1) in emit2() argument 73 fpi->U.I.SrcReg[0] = SrcReg0; in emit2() 82 struct rc_src_register SrcReg0, struct rc_src_register SrcReg1, in emit3() argument 93 fpi->U.I.SrcReg[0] = SrcReg0; in emit3()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
D | X86InstructionSelector.cpp | 1254 unsigned SrcReg0 = I.getOperand(1).getReg(); in selectMergeValues() local 1257 const LLT SrcTy = MRI.getType(SrcReg0); in selectMergeValues()
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