Searched refs:SrcReg0Sub1 (Results 1 – 2 of 2) sorted by relevance
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 2726 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitUnaryOp() local
2731 .addOperand(SrcReg0Sub1); in splitScalar64BitUnaryOp()
2788 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitBinaryOp() local
2795 .addOperand(SrcReg0Sub1) in splitScalar64BitBinaryOp()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 4205 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitUnaryOp() local
4209 BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1); in splitScalar64BitUnaryOp()
4258 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitAddSub() local
4274 .add(SrcReg0Sub1) in splitScalar64BitAddSub()
4334 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC, in splitScalar64BitBinaryOp() local
4341 .add(SrcReg0Sub1) in splitScalar64BitBinaryOp()
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