Searched refs:SrcReg1Sub0 (Results 1 – 2 of 2) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 4254 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, in splitScalar64BitAddSub() local
4268 .add(SrcReg1Sub0); in splitScalar64BitAddSub()
4322 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, in splitScalar64BitBinaryOp() local
4332 .add(SrcReg1Sub0); in splitScalar64BitBinaryOp()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 2776 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC, in splitScalar64BitBinaryOp() local
2786 .addOperand(SrcReg1Sub0); in splitScalar64BitBinaryOp()
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