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Searched refs:Srm (Results 1 – 7 of 7) sorted by relevance

/external/syzkaller/pkg/ifuzz/
Ddecode.go128 if insn.Srm && i == len(insn.Opcode)-1 {
Dencode.go156 if insn.Srm {
Difuzz.go37 Srm bool // register is embed in the first byte member
/external/syzkaller/pkg/ifuzz/gen/
Dgen.go261 insn.Srm = true
/external/syzkaller/pkg/ifuzz/generated/
Dinsns.go459 …{Name: "INC", Extension: "BASE", Mode: 14, Opcode: []uint8{64}, Mod: -100, Reg: -100, Rm: -1, Srm:…
460 …{Name: "DEC", Extension: "BASE", Mode: 14, Opcode: []uint8{72}, Mod: -100, Reg: -100, Rm: -1, Srm:…
461 …{Name: "PUSH", Extension: "BASE", Mode: 15, Opcode: []uint8{80}, Mod: -100, Reg: -100, Rm: -1, Srm…
462 …{Name: "POP", Extension: "BASE", Mode: 15, Opcode: []uint8{88}, Mod: -100, Reg: -100, Rm: -1, Srm:…
538 …{Name: "NOP", Extension: "BASE", Mode: 15, Opcode: []uint8{144}, Mod: -100, Reg: -100, Srm: true, …
539 …ode: 15, Opcode: []uint8{144}, Prefix: []uint8{243}, Mod: -100, Reg: -100, Srm: true, NoRepPrefix:…
540 …ode: 15, Opcode: []uint8{144}, Prefix: []uint8{243}, Mod: -100, Reg: -100, Srm: true, NoRepPrefix:…
541 …ension: "BASE", Mode: 15, Opcode: []uint8{144}, Mod: -100, Reg: -100, Rm: -1, Srm: true, VexP: -1},
625 …{Name: "MOV", Extension: "BASE", Mode: 15, Opcode: []uint8{176}, Mod: -100, Reg: -100, Rm: -1, Srm…
626 …{Name: "MOV", Extension: "BASE", Mode: 15, Opcode: []uint8{184}, Mod: -100, Reg: -100, Rm: -1, Srm…
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86GenAsmWriter.inc5877 "Srm\000FsANDPSrr\000FsFLD0SD\000FsFLD0SS\000FsMOVAPDrm\000FsMOVAPDrr\000"
DX86GenAsmWriter1.inc6620 "Srm\000FsANDPSrr\000FsFLD0SD\000FsFLD0SS\000FsMOVAPDrm\000FsMOVAPDrr\000"