| /external/clang/test/CodeGenObjC/ |
| D | category-super-class-meth.m | 15 @interface Sub2 : NSObject @end interface
17 @interface Sub2 (Category) @end interface in Category
19 @implementation Sub2 (Category) implementation in Category
24 // CHECK: define internal i8* @"\01+[Sub2(Category) copy]
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| /external/snakeyaml/src/test/java/org/yaml/snakeyaml/ruby/ |
| D | TestObject.java | 20 private Sub2 sub2;
30 public Sub2 getSub2() { in getSub2()
34 public void setSub2(Sub2 sub2) { in setSub2()
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| D | RubyTest.java | 63 repr.addClassTag(Sub2.class, new Tag("!ruby/object:Test::Module::Sub2")); in testEmitWithTags()
86 repr.addClassTag(Sub2.class, new Tag("!ruby/object:Test::Module::Sub2")); in testEmitWithTags2WithoutTagForParentJavabean()
108 con.addTypeDescription(new TypeDescription(Sub2.class, "!ruby/object:Test::Module::Sub2")); in parseObject()
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| D | Sub2.java | 20 public class Sub2 { class
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| /external/tensorflow/tensorflow/python/kernel_tests/distributions/ |
| D | kullback_leibler_test.py | 106 class Sub2(normal.Normal): class
121 @kullback_leibler.RegisterKL(Sub1, Sub2)
125 @kullback_leibler.RegisterKL(Sub2, Sub1)
132 sub2 = Sub2(loc=0.0, scale=1.0)
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| /external/clang/test/Index/ |
| D | annotate-module.m | 32 …] inclusion directive=[[INC_DIR:Module[/\\]Sub2\.h \(.*/Modules/Inputs/Module\.framework[/\\]Heade…
37 // CHECK-MOD-NEXT: Identifier: "Sub2" [1:18 - 1:22] inclusion directive=[[INC_DIR]]
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| D | index-module.m | 48 // CHECK-TMOD-NEXT: [ppIncludedFile]: [[TMODHDR]]Sub2.h | name: "Module/Sub2.h" | hash loc: [[TMODH…
62 …on]: kind: variable | name: Module_Sub2 | USR: c:@Module_Sub2 | {{.*}} | loc: [[TMODHDR]]Sub2.h:1:6
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| /external/clang/test/CodeGenObjCXX/ |
| D | encode.mm | 142 struct Sub2 : public Sub_with_virt, public Base1, virtual DBase { struct
155 // CHECK: @g4 = constant [19 x i8] c"{Sub2=^^?qcf^^?cd}\00"
156 extern const char g4[] = @encode(Sub2);
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| /external/clang/test/Modules/Inputs/ |
| D | MethodPoolASub2.h | 1 @interface A (Sub2)
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| D | module.map | 139 explicit module Sub2 {
150 explicit module Sub2 {
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| /external/clang/test/Modules/ |
| D | submodules.m | 6 // Note: transitively imports Module.Sub2.
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| D | dependency-dump.m | 13 // VFS: 'name': "Sub2.h"
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| D | dependency-dump-dependent-module.m | 14 // VFS: 'name': "Sub2.h"
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| /external/llvm/test/TableGen/ |
| D | SuperSubclassSameName.td | 21 class Sub2<int F> : Super2<F>;
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| /external/swiftshader/third_party/LLVM/test/TableGen/ |
| D | SuperSubclassSameName.td | 21 class Sub2<int F> : Super2<F>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/ |
| D | SuperSubclassSameName.td | 21 class Sub2<int F> : Super2<F>;
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| /external/clang/test/FixIt/ |
| D | typo.m | 116 @interface Sub2 : Super interface
120 @implementation Sub2 implementation
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| /external/clang/test/ARCMT/Inputs/ |
| D | module.map | 134 explicit module Sub2 {
145 explicit module Sub2 {
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonHardwareLoops.cpp | 1510 unsigned Sub2 = DI->getOperand(2).getImm(); in checkForImmediate() local
1512 if (Sub2 == Hexagon::subreg_loreg && Sub4 == Hexagon::subreg_hireg) in checkForImmediate()
1514 else if (Sub2 == Hexagon::subreg_hireg && Sub4 == Hexagon::subreg_loreg) in checkForImmediate()
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| D | HexagonBitSimplify.cpp | 392 unsigned Sub1 = I.getOperand(2).getImm(), Sub2 = I.getOperand(4).getImm(); in parseRegSequence() local
393 assert(Sub1 != Sub2); in parseRegSequence()
394 if (Sub1 == Hexagon::subreg_loreg && Sub2 == Hexagon::subreg_hireg) { in parseRegSequence()
399 if (Sub1 == Hexagon::subreg_hireg && Sub2 == Hexagon::subreg_loreg) { in parseRegSequence()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonHardwareLoops.cpp | 1550 unsigned Sub2 = DI->getOperand(2).getImm(); in checkForImmediate() local
1552 if (Sub2 == Hexagon::isub_lo && Sub4 == Hexagon::isub_hi) in checkForImmediate()
1554 else if (Sub2 == Hexagon::isub_hi && Sub4 == Hexagon::isub_lo) in checkForImmediate()
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| D | HexagonBitSimplify.cpp | 439 unsigned Sub1 = I.getOperand(2).getImm(), Sub2 = I.getOperand(4).getImm(); in parseRegSequence() local
445 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo)); in parseRegSequence()
446 if (Sub1 == SubLo && Sub2 == SubHi) { in parseRegSequence()
451 if (Sub1 == SubHi && Sub2 == SubLo) { in parseRegSequence()
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| D | HexagonConstPropagation.cpp | 1941 unsigned Sub2 = MI.getOperand(4).getImm(); in evaluate() local
1947 if (Sub2 != SubLo && Sub2 != SubHi) in evaluate()
1949 assert(Sub1 != Sub2); in evaluate()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 1681 SDValue Sub2 = DAG.getBitcast(VT, in LowerUDIVREM64() local
1710 SDValue Sel2 = DAG.getSelectCC(DL, C6, Zero, Sub3, Sub2, ISD::SETNE); in LowerUDIVREM64()
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| /external/antlr/tool/ |
| D | CHANGES.txt | 210 import Sub1, Sub2;
|