Home
last modified time | relevance | path

Searched refs:SubIdx (Results 1 – 25 of 136) sorted by relevance

123456

/external/llvm/lib/CodeGen/
DDetectDeadLanes.cpp245 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferUsedLanes() local
246 return TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
249 unsigned SubIdx = MI.getOperand(3).getImm(); in transferUsedLanes() local
251 TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
260 MO1UsedLanes = UsedLanes & ~TRI->getSubRegIndexLaneMask(SubIdx); in transferUsedLanes()
269 unsigned SubIdx = MI.getOperand(2).getImm(); in transferUsedLanes() local
270 return TRI->composeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
319 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferDefinedLanes() local
320 DefinedLanes = TRI->composeSubRegIndexLaneMask(SubIdx, DefinedLanes); in transferDefinedLanes()
321 DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx); in transferDefinedLanes()
[all …]
DTargetRegisterInfo.cpp46 unsigned SubIdx) { in PrintReg() argument
47 return Printable([Reg, TRI, SubIdx](raw_ostream &OS) { in PrintReg()
58 if (SubIdx) { in PrintReg()
60 OS << ':' << TRI->getSubRegIndexName(SubIdx); in PrintReg()
62 OS << ":sub(" << SubIdx << ')'; in PrintReg()
DExpandPostRAPseudos.cpp90 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
92 assert(SubIdx != 0 && "Invalid index for insert_subreg"); in LowerSubregToReg()
93 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DDetectDeadLanes.cpp243 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferUsedLanes() local
244 return TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
247 unsigned SubIdx = MI.getOperand(3).getImm(); in transferUsedLanes() local
249 TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
258 MO1UsedLanes = UsedLanes & ~TRI->getSubRegIndexLaneMask(SubIdx); in transferUsedLanes()
267 unsigned SubIdx = MI.getOperand(2).getImm(); in transferUsedLanes() local
268 return TRI->composeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
317 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferDefinedLanes() local
318 DefinedLanes = TRI->composeSubRegIndexLaneMask(SubIdx, DefinedLanes); in transferDefinedLanes()
319 DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx); in transferDefinedLanes()
[all …]
DExpandPostRAPseudos.cpp86 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
88 assert(SubIdx != 0 && "Invalid index for insert_subreg"); in LowerSubregToReg()
89 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DRegisterCoalescer.h42 unsigned SubIdx; variable
60 : TII(tii), TRI(tri), DstReg(0), SrcReg(0), SubIdx(0), in CoalescerPair()
99 unsigned getSubIdx() const { return SubIdx; } in getSubIdx()
DExpandPostRAPseudos.cpp110 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
112 assert(SubIdx != 0 && "Invalid index for insert_subreg"); in LowerSubregToReg()
113 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
DVirtRegRewriter.cpp706 unsigned SubIdx, const TargetRegisterInfo *TRI) { in findSuperReg() argument
710 if (TRI->getSubReg(Reg, SubIdx) == SubReg) in findSuperReg()
914 unsigned SubIdx = 0; in GetRegForReload() local
919 SubIdx = TRI->getSubRegIndex(PRRU, RealPhysRegUsed); in GetRegForReload()
920 assert(SubIdx && in GetRegForReload()
956 unsigned RReg = SubIdx ? TRI->getSubReg(NewPhysReg, SubIdx) :NewPhysReg; in GetRegForReload()
1975 unsigned SubIdx = MI.getOperand(i).getSubReg(); in ProcessUses() local
2022 if (PhysReg && !AvoidReload && SubIdx) { in ProcessUses()
2070 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; in ProcessUses()
2156 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; in ProcessUses()
[all …]
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetRegisterInfo.h324 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName() argument
325 assert(SubIdx && "This is not a subregister index"); in getSubRegIndexName()
326 return SubRegIndexNames[SubIdx-1]; in getSubRegIndexName()
382 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg() argument
385 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR)) in getMatchingSuperReg()
703 unsigned SubIdx; variable
706 : TRI(tri), Reg(reg), SubIdx(subidx) {} in TRI()
/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h370 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName() argument
371 assert(SubIdx && SubIdx < getNumSubRegIndices() && in getSubRegIndexName()
373 return SubRegIndexNames[SubIdx-1]; in getSubRegIndexName()
380 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask() argument
381 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index"); in getSubRegIndexLaneMask()
382 return SubRegIndexLaneMasks[SubIdx]; in getSubRegIndexLaneMask()
499 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg() argument
501 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); in getMatchingSuperReg()
DTargetInstrInfo.h171 unsigned &SubIdx) const { in isCoalescableExtInstr() argument
250 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
281 unsigned SubIdx, const MachineInstr &Orig,
367 unsigned SubIdx; member
369 unsigned SubIdx = 0)
370 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h381 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName() argument
382 assert(SubIdx && SubIdx < getNumSubRegIndices() && in getSubRegIndexName()
384 return SubRegIndexNames[SubIdx-1]; in getSubRegIndexName()
391 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask() argument
392 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index"); in getSubRegIndexLaneMask()
393 return SubRegIndexLaneMasks[SubIdx]; in getSubRegIndexLaneMask()
534 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg() argument
536 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); in getMatchingSuperReg()
1170 unsigned SubIdx = 0,
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DCodeGenRegisters.cpp134 CodeGenSubRegIndex *SubIdx = *I; in computeConcatTransitiveClosure() local
135 SubIdx->computeConcatTransitiveClosure(); in computeConcatTransitiveClosure()
137 for (CodeGenSubRegIndex *SRI : SubIdx->ConcatenationOf) in computeConcatTransitiveClosure()
141 if (SubIdx->ConcatenationOf.empty()) { in computeConcatTransitiveClosure()
145 I = ConcatenationOf.insert(I, SubIdx->ConcatenationOf.begin(), in computeConcatTransitiveClosure()
146 SubIdx->ConcatenationOf.end()); in computeConcatTransitiveClosure()
147 I += SubIdx->ConcatenationOf.size(); in computeConcatTransitiveClosure()
502 for (CodeGenSubRegIndex *SubIdx : SubRegIdx->ConcatenationOf) in computeSecondarySubRegs()
503 Parts.push_back(SubIdx); in computeSecondarySubRegs()
537 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second); in computeSecondarySubRegs() local
[all …]
DCodeGenRegisters.h376 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg() argument
377 return SubClassWithSubReg.lookup(SubIdx); in getSubClassWithSubReg()
390 const CodeGenSubRegIndex *SubIdx) const;
392 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx, in setSubClassWithSubReg() argument
394 SubClassWithSubReg[SubIdx] = SubRC; in setSubClassWithSubReg()
399 void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
403 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, in addSuperRegClass() argument
405 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()
/external/swiftshader/third_party/LLVM/utils/TableGen/
DCodeGenRegisters.h153 CodeGenRegisterClass *getSubClassWithSubReg(Record *SubIdx) const { in getSubClassWithSubReg() argument
154 return SubClassWithSubReg.lookup(SubIdx); in getSubClassWithSubReg()
157 void setSubClassWithSubReg(Record *SubIdx, CodeGenRegisterClass *SubRC) { in setSubClassWithSubReg() argument
158 SubClassWithSubReg[SubIdx] = SubRC; in setSubClassWithSubReg()
/external/swiftshader/third_party/LLVM/lib/Target/
DTargetRegisterInfo.cpp43 if (SubIdx) { in print()
45 OS << ':' << TRI->getSubRegIndexName(SubIdx); in print()
47 OS << ":sub(" << SubIdx << ')'; in print()
/external/llvm/utils/TableGen/
DCodeGenRegisters.h349 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg() argument
350 return SubClassWithSubReg.lookup(SubIdx); in getSubClassWithSubReg()
353 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx, in setSubClassWithSubReg() argument
355 SubClassWithSubReg[SubIdx] = SubRC; in setSubClassWithSubReg()
360 void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
364 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, in addSuperRegClass() argument
366 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()
DCodeGenRegisters.cpp469 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second); in computeSecondarySubRegs() local
470 if (!SubIdx) in computeSecondarySubRegs()
473 NewIdx->addComposite(SI->first, SubIdx); in computeSecondarySubRegs()
898 void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx, in getSuperRegClasses() argument
900 auto FindI = SuperRegClasses.find(SubIdx); in getSuperRegClasses()
1565 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); in pruneUnitSets() local
1566 SubIdx != EndIdx; ++SubIdx) { in pruneUnitSets()
1567 const RegUnitSet &SubSet = RegUnitSets[SubIdx]; in pruneUnitSets()
1570 if (SuperIdx == SubIdx) in pruneUnitSets()
1579 DEBUG(dbgs() << "UnitSet " << SubIdx << " subsumed by " << SuperIdx in pruneUnitSets()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstructionSelector.cpp204 unsigned SubIdx = X86::NoSubRegister; in getSubRegIndex() local
206 SubIdx = X86::sub_32bit; in getSubRegIndex()
208 SubIdx = X86::sub_16bit; in getSubRegIndex()
210 SubIdx = X86::sub_8bit; in getSubRegIndex()
213 return SubIdx; in getSubRegIndex()
723 unsigned SubIdx; in selectTruncOrPtrToInt() local
726 SubIdx = X86::NoSubRegister; in selectTruncOrPtrToInt()
728 SubIdx = X86::sub_32bit; in selectTruncOrPtrToInt()
730 SubIdx = X86::sub_16bit; in selectTruncOrPtrToInt()
732 SubIdx = X86::sub_8bit; in selectTruncOrPtrToInt()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DThumb2RegisterInfo.cpp38 unsigned DestReg, unsigned SubIdx, in emitLoadConstPool() argument
49 .addReg(DestReg, getDefRegState(true), SubIdx) in emitLoadConstPool()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp400 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, in ConstrainForSubReg() argument
403 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
416 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); in ConstrainForSubReg()
451 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); in EmitSubregNode() local
459 SubIdx == DefSubIdx) { in EmitSubregNode()
472 VReg = ConstrainForSubReg(VReg, SubIdx, in EmitSubregNode()
482 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx); in EmitSubregNode()
489 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode() local
506 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); in EmitSubregNode()
527 MI->addOperand(MachineOperand::CreateImm(SubIdx)); in EmitSubregNode()
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp444 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, in ConstrainForSubReg() argument
447 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
460 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); in ConstrainForSubReg()
493 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); in EmitSubregNode() local
502 SubIdx == DefSubIdx && in EmitSubregNode()
517 VReg = ConstrainForSubReg(VReg, SubIdx, in EmitSubregNode()
527 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx); in EmitSubregNode()
534 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode() local
551 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); in EmitSubregNode()
572 MIB.addImm(SubIdx); in EmitSubregNode()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp467 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, in ConstrainForSubReg() argument
470 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
483 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); in ConstrainForSubReg()
516 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); in EmitSubregNode() local
534 SubIdx == DefSubIdx && in EmitSubregNode()
550 Reg = ConstrainForSubReg(Reg, SubIdx, in EmitSubregNode()
563 CopyMI.addReg(Reg, 0, SubIdx); in EmitSubregNode()
565 CopyMI.addReg(TRI->getSubReg(Reg, SubIdx)); in EmitSubregNode()
572 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode() local
589 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); in EmitSubregNode()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DThumbRegisterInfo.cpp65 unsigned SubIdx, int Val, in emitThumb1LoadConstPool() argument
77 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
85 unsigned SubIdx, int Val, in emitThumb2LoadConstPool() argument
96 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
106 const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, in emitLoadConstPool() argument
113 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
116 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
/external/llvm/lib/Target/ARM/
DThumbRegisterInfo.cpp65 unsigned SubIdx, int Val, in emitThumb1LoadConstPool() argument
77 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
85 unsigned SubIdx, int Val, in emitThumb2LoadConstPool() argument
96 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
105 const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, in emitLoadConstPool() argument
112 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
115 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()

123456