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Searched refs:SubReg (Results 1 – 25 of 103) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
DConcatenatedSubregs.td103 // CHECK-NEXT: SubReg ssub0 = S0
104 // CHECK-NEXT: SubReg ssub1 = S1
108 // CHECK-NEXT: SubReg ssub0 = S9
109 // CHECK-NEXT: SubReg ssub1 = S10
110 // CHECK-NEXT: SubReg ssub2 = S11
111 // CHECK-NEXT: SubReg ssub3 = S12
112 // CHECK-NEXT: SubReg ssub4 = S13
113 // CHECK-NEXT: SubReg sub0 = S9_S10
114 // CHECK-NEXT: SubReg sub1 = S11_S12
115 // CHECK-NEXT: SubReg ssub1_ssub2 = D5
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/external/swiftshader/third_party/LLVM/lib/CodeGen/
DLiveVariables.cpp194 unsigned SubReg = *SubRegs; ++SubRegs) { in FindLastPartialDef()
195 MachineInstr *Def = PhysRegDef[SubReg]; in FindLastPartialDef()
200 LastDefReg = SubReg; in FindLastPartialDef()
218 unsigned SubReg = *SubRegs; ++SubRegs) in FindLastPartialDef()
219 PartDefRegs.insert(SubReg); in FindLastPartialDef()
249 unsigned SubReg = *SubRegs; ++SubRegs) { in HandlePhysRegUse()
250 if (Processed.count(SubReg)) in HandlePhysRegUse()
252 if (PartDefRegs.count(SubReg)) in HandlePhysRegUse()
256 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
259 PhysRegDef[SubReg] = LastPartialDef; in HandlePhysRegUse()
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DRegisterScavenging.cpp41 unsigned SubReg = *SubRegs; ++SubRegs) in setUsed()
42 RegsAvailable.reset(SubReg); in setUsed()
203 unsigned SubReg = *SubRegs; ++SubRegs) in forward()
204 if (isUsed(SubReg)) { in forward()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DLiveVariables.cpp198 unsigned SubReg = *SubRegs; in FindLastPartialDef() local
199 MachineInstr *Def = PhysRegDef[SubReg]; in FindLastPartialDef()
204 LastDefReg = SubReg; in FindLastPartialDef()
252 unsigned SubReg = *SubRegs; in HandlePhysRegUse() local
253 if (Processed.count(SubReg)) in HandlePhysRegUse()
255 if (PartDefRegs.count(SubReg)) in HandlePhysRegUse()
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
262 PhysRegDef[SubReg] = LastPartialDef; in HandlePhysRegUse()
263 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS) in HandlePhysRegUse()
291 unsigned SubReg = *SubRegs; in FindLastRefOrPartRef() local
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DPeepholeOptimizer.cpp294 ValueTrackerResult(unsigned Reg, unsigned SubReg) { in ValueTrackerResult() argument
295 addSource(Reg, SubReg); in ValueTrackerResult()
330 return RegSrcs[Idx].SubReg; in getSrcSubReg()
682 ValueTracker ValTracker(CurSrcPair.Reg, CurSrcPair.SubReg, *MRI, TII); in findNextSource()
732 if (!TRI->shouldRewriteCopySrc(DefRC, RegSubReg.SubReg, SrcRC, in findNextSource()
733 CurSrcPair.SubReg)) in findNextSource()
738 if (PHICount > 0 && CurSrcPair.SubReg != 0) in findNextSource()
764 assert(SrcRegs[0].SubReg == 0 && "should not have subreg operand"); in insertPHI()
772 MIB.addReg(RegPair.Reg, 0, RegPair.SubReg); in insertPHI()
1054 if ((Src.SubReg = MOInsertedReg.getSubReg())) in getNextRewritableSource()
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DDetectDeadLanes.cpp178 unsigned SubReg = MI.getOperand(2).getImm(); in isCrossCopy() local
179 SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx); in isCrossCopy()
428 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes() local
451 if (SubReg == 0) in determineInitialUsedLanes()
454 UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg); in determineInitialUsedLanes()
461 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput() local
462 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg); in isUndefRegAtInput()
DLiveRangeCalc.cpp87 unsigned SubReg = MO.getSubReg(); in calculate() local
88 if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) { in calculate()
89 LaneBitmask SubMask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg) in calculate()
177 unsigned SubReg = MO.getSubReg(); in extendToUses() local
178 if (SubReg != 0) { in extendToUses()
179 LaneBitmask SLM = TRI.getSubRegIndexLaneMask(SubReg); in extendToUses()
/external/llvm/lib/CodeGen/
DLiveVariables.cpp198 unsigned SubReg = *SubRegs; in FindLastPartialDef() local
199 MachineInstr *Def = PhysRegDef[SubReg]; in FindLastPartialDef()
204 LastDefReg = SubReg; in FindLastPartialDef()
252 unsigned SubReg = *SubRegs; in HandlePhysRegUse() local
253 if (Processed.count(SubReg)) in HandlePhysRegUse()
255 if (PartDefRegs.count(SubReg)) in HandlePhysRegUse()
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
262 PhysRegDef[SubReg] = LastPartialDef; in HandlePhysRegUse()
263 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS) in HandlePhysRegUse()
291 unsigned SubReg = *SubRegs; in FindLastRefOrPartRef() local
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DPeepholeOptimizer.cpp160 bool findNextSource(unsigned Reg, unsigned SubReg,
225 ValueTrackerResult(unsigned Reg, unsigned SubReg) : Inst(nullptr) { in ValueTrackerResult() argument
226 addSource(Reg, SubReg); in ValueTrackerResult()
257 return RegSrcs[Idx].SubReg; in getSrcSubReg()
616 bool PeepholeOptimizer::findNextSource(unsigned Reg, unsigned SubReg, in findNextSource() argument
627 TargetInstrInfo::RegSubRegPair CurSrcPair(Reg, SubReg); in findNextSource()
638 ValueTracker ValTracker(CurSrcPair.Reg, CurSrcPair.SubReg, *MRI, in findNextSource()
676 CurSrcPair.SubReg = Res.getSrcSubReg(0); in findNextSource()
685 ShouldRewrite = TRI->shouldRewriteCopySrc(DefRC, SubReg, SrcRC, in findNextSource()
686 CurSrcPair.SubReg); in findNextSource()
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DLiveRangeCalc.cpp65 unsigned SubReg = MO.getSubReg(); in calculate() local
66 if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) { in calculate()
67 LaneBitmask Mask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg) in calculate()
175 unsigned SubReg = MO.getSubReg(); in extendToUses() local
176 if (SubReg != 0) { in extendToUses()
177 LaneBitmask SubRegMask = TRI.getSubRegIndexLaneMask(SubReg); in extendToUses()
DDetectDeadLanes.cpp180 unsigned SubReg = MI.getOperand(2).getImm(); in isCrossCopy() local
181 SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx); in isCrossCopy()
430 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes() local
453 if (SubReg == 0) in determineInitialUsedLanes()
456 UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg); in determineInitialUsedLanes()
463 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput() local
464 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg); in isUndefRegAtInput()
/external/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp112 static bool isGPR64(unsigned Reg, unsigned SubReg, in isGPR64() argument
114 if (SubReg) in isGPR64()
121 static bool isFPR64(unsigned Reg, unsigned SubReg, in isFPR64() argument
125 SubReg == 0) || in isFPR64()
127 SubReg == AArch64::dsub); in isFPR64()
129 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) || in isFPR64()
130 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub); in isFPR64()
137 unsigned &SubReg) { in getSrcFromCopy() argument
138 SubReg = 0; in getSrcFromCopy()
146 SubReg = AArch64::dsub; in getSrcFromCopy()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp105 static bool isGPR64(unsigned Reg, unsigned SubReg, in isGPR64() argument
107 if (SubReg) in isGPR64()
114 static bool isFPR64(unsigned Reg, unsigned SubReg, in isFPR64() argument
118 SubReg == 0) || in isFPR64()
120 SubReg == AArch64::dsub); in isFPR64()
122 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) || in isFPR64()
123 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub); in isFPR64()
130 unsigned &SubReg) { in getSrcFromCopy() argument
131 SubReg = 0; in getSrcFromCopy()
139 SubReg = AArch64::dsub; in getSrcFromCopy()
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsExpandPseudo.cpp92 const unsigned* SubReg = in ExpandBuildPairF64() local
97 BuildMI(MBB, I, dl, Mtc1Tdd, *SubReg).addReg(LoReg); in ExpandBuildPairF64()
98 BuildMI(MBB, I, dl, Mtc1Tdd, *(SubReg + 1)).addReg(HiReg); in ExpandBuildPairF64()
108 const unsigned* SubReg = TM.getRegisterInfo()->getSubRegisters(SrcReg); in ExpandExtractElementF64() local
110 BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(*(SubReg + N)); in ExpandExtractElementF64()
/external/llvm/lib/MC/
DMCRegisterInfo.cpp38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const { in getSubRegIndex()
39 assert(SubReg && SubReg < getNumRegs() && "This is not a register"); in getSubRegIndex()
44 if (*Subs == SubReg) in getSubRegIndex()
/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td36 class GP8<GPR SubReg, string n> : PPCReg<n> {
37 let HWEncoding = SubReg.HWEncoding;
38 let SubRegs = [SubReg];
53 class QFPR<FPR SubReg, string n> : PPCReg<n> {
54 let HWEncoding = SubReg.HWEncoding;
55 let SubRegs = [SubReg];
67 class VR<VF SubReg, string n> : PPCReg<n> {
68 let HWEncoding{4-0} = SubReg.HWEncoding{4-0};
70 let SubRegs = [SubReg];
76 class VSRL<FPR SubReg, string n> : PPCReg<n> {
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/MC/
DMCRegisterInfo.cpp43 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const { in getSubRegIndex()
44 assert(SubReg && SubReg < getNumRegs() && "This is not a register"); in getSubRegIndex()
49 if (*Subs == SubReg) in getSubRegIndex()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td35 class GP8<GPR SubReg, string n> : PPCReg<n> {
36 let HWEncoding = SubReg.HWEncoding;
37 let SubRegs = [SubReg];
42 class SPE<GPR SubReg, string n> : PPCReg<n> {
43 let HWEncoding = SubReg.HWEncoding;
44 let SubRegs = [SubReg];
59 class QFPR<FPR SubReg, string n> : PPCReg<n> {
60 let HWEncoding = SubReg.HWEncoding;
61 let SubRegs = [SubReg];
73 class VR<VF SubReg, string n> : PPCReg<n> {
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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DMachineOperand.h62 unsigned char SubReg; variable
228 return (unsigned)SubReg; in getSubReg()
297 SubReg = (unsigned char)subReg; in setSubReg()
493 unsigned SubReg = 0,
506 Op.SubReg = SubReg;
/external/llvm/include/llvm/Target/
DTargetInstrInfo.h359 unsigned SubReg; member
360 RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
361 : Reg(Reg), SubReg(SubReg) {} in Reg()
368 RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
370 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair()
1504 std::make_pair(Val.Reg, Val.SubReg);
1510 RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
DTargetRegisterInfo.h921 unsigned SubReg, in shouldCoalesce() argument
954 unsigned SubReg; variable
965 SubReg(0),
976 unsigned getSubReg() const { return SubReg; } in getSubReg()
987 SubReg = *Idx++;
988 if (!SubReg)
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DTargetInstrInfo.h428 unsigned SubReg; member
430 RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
431 : Reg(Reg), SubReg(SubReg) {} in Reg()
440 RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
442 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair()
1682 std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
1689 RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
DMachineInstrBuilder.h85 unsigned SubReg = 0) const {
95 SubReg,
104 unsigned SubReg = 0) const {
105 return addReg(RegNo, Flags | RegState::Define, SubReg);
111 unsigned SubReg = 0) const {
114 return addReg(RegNo, Flags, SubReg);
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIFormMemoryClauses.cpp364 forAllLanes(R.first, R.second.second, [&R, &B](unsigned SubReg) { in runOnMachineFunction() argument
366 if (!SubReg) in runOnMachineFunction()
368 B.addDef(R.first, S, SubReg); in runOnMachineFunction()
373 forAllLanes(R.first, R.second.second, [&R, &B](unsigned SubReg) { in runOnMachineFunction() argument
374 B.addUse(R.first, R.second.first & ~RegState::Kill, SubReg); in runOnMachineFunction()
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DCodeGenRegisters.cpp257 for (const auto &SubReg : SubRegs) { in inheritRegUnits() local
258 CodeGenRegister *SR = SubReg.second; in inheritRegUnits()
352 for (const auto &SubReg : Map) in computeSubRegs() local
353 if (Orphans.erase(SubReg.second)) in computeSubRegs()
354 SubRegs[RegBank.getCompositeSubRegIndex(Idx, SubReg.first)] = SubReg.second; in computeSubRegs()
358 for (const auto &SubReg : SubRegs) { in computeSubRegs() local
359 if (SubReg.second == this) { in computeSubRegs()
369 SubReg.first->AllSuperRegsCovered = false; in computeSubRegs()
373 SubReg2Idx.insert(std::make_pair(SubReg.second, SubReg.first)).first; in computeSubRegs()
374 if (Ins->second == SubReg.first) in computeSubRegs()
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