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Searched refs:SuperRC (Results 1 – 25 of 25) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DMachineCopyPropagation.cpp287 const TargetRegisterClass *SuperRC = UseDstRC; in isForwardableRegClassCopy() local
289 SuperRC; SuperRC = *SuperRCI++) in isForwardableRegClassCopy()
290 if (SuperRC->contains(CopySrcReg)) in isForwardableRegClassCopy()
DAggressiveAntiDepBreaker.cpp630 const TargetRegisterClass *SuperRC = in FindSuitableFreeRegisters() local
633 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
641 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size())); in FindSuitableFreeRegisters()
643 unsigned OrigR = RenameOrder[SuperRC]; in FindSuitableFreeRegisters()
737 RenameOrder.erase(SuperRC); in FindSuitableFreeRegisters()
738 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R)); in FindSuitableFreeRegisters()
DRegAllocGreedy.cpp2025 const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC, in getNumAllocatableRegsForConstraints() argument
2028 assert(SuperRC && "Invalid register class"); in getNumAllocatableRegsForConstraints()
2031 MI->getRegClassConstraintEffectForVReg(Reg, SuperRC, TII, TRI, in getNumAllocatableRegsForConstraints()
2065 const TargetRegisterClass *SuperRC = in tryInstructionSplit() local
2067 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC); in tryInstructionSplit()
2076 getNumAllocatableRegsForConstraints(MI, VirtReg.reg, SuperRC, TII, in tryInstructionSplit()
DTargetLoweringBase.cpp1047 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); in findRepresentativeClass() local
1049 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC)) in findRepresentativeClass()
1051 if (!isLegalRC(*TRI, *SuperRC)) in findRepresentativeClass()
1053 BestRC = SuperRC; in findRepresentativeClass()
DMachineVerifier.cpp1295 const TargetRegisterClass *SuperRC = in visitMachineOperand() local
1297 if (!SuperRC) { in visitMachineOperand()
1301 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSILoadStoreOptimizer.cpp510 const TargetRegisterClass *SuperRC in mergeRead2Pair() local
512 unsigned DestReg = MRI->createVirtualRegister(SuperRC); in mergeRead2Pair()
646 const TargetRegisterClass *SuperRC = in mergeSBufferLoadImmPair() local
648 unsigned DestReg = MRI->createVirtualRegister(SuperRC); in mergeSBufferLoadImmPair()
698 const TargetRegisterClass *SuperRC = in mergeBufferLoadPair() local
700 unsigned DestReg = MRI->createVirtualRegister(SuperRC); in mergeBufferLoadPair()
792 const TargetRegisterClass *SuperRC = in mergeBufferStorePair() local
794 unsigned SrcReg = MRI->createVirtualRegister(SuperRC); in mergeBufferStorePair()
DSIInstrInfo.h70 const TargetRegisterClass *SuperRC,
76 const TargetRegisterClass *SuperRC,
DAMDGPUISelDAGToDAG.cpp341 const TargetRegisterClass *SuperRC = in getOperandRegClass() local
346 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC, in getOperandRegClass()
DSIInstrInfo.cpp3102 const TargetRegisterClass *SuperRC, in buildExtractSubReg() argument
3120 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC); in buildExtractSubReg()
3135 const TargetRegisterClass *SuperRC, in buildExtractSubRegOrImm() argument
3147 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC, in buildExtractSubRegOrImm()
DSIISelLowering.cpp2967 const TargetRegisterClass *SuperRC, in computeIndirectRegAndOffset() argument
2970 int NumElts = TRI.getRegSizeInBits(*SuperRC) / 32; in computeIndirectRegAndOffset()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DAggressiveAntiDepBreaker.cpp620 const TargetRegisterClass *SuperRC = in FindSuitableFreeRegisters() local
623 ArrayRef<unsigned> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
631 if (RenameOrder.count(SuperRC) == 0) in FindSuitableFreeRegisters()
632 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size())); in FindSuitableFreeRegisters()
634 unsigned OrigR = RenameOrder[SuperRC]; in FindSuitableFreeRegisters()
701 RenameOrder.erase(SuperRC); in FindSuitableFreeRegisters()
702 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R)); in FindSuitableFreeRegisters()
DMachineVerifier.cpp770 const TargetRegisterClass *SuperRC = in visitMachineOperand() local
772 if (!SuperRC) { in visitMachineOperand()
776 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
/external/llvm/lib/CodeGen/
DAggressiveAntiDepBreaker.cpp611 const TargetRegisterClass *SuperRC = in FindSuitableFreeRegisters() local
614 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
622 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size())); in FindSuitableFreeRegisters()
624 unsigned OrigR = RenameOrder[SuperRC]; in FindSuitableFreeRegisters()
717 RenameOrder.erase(SuperRC); in FindSuitableFreeRegisters()
718 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R)); in FindSuitableFreeRegisters()
DRegAllocGreedy.cpp1560 const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC, in getNumAllocatableRegsForConstraints() argument
1563 assert(SuperRC && "Invalid register class"); in getNumAllocatableRegsForConstraints()
1566 MI->getRegClassConstraintEffectForVReg(Reg, SuperRC, TII, TRI, in getNumAllocatableRegsForConstraints()
1599 const TargetRegisterClass *SuperRC = in tryInstructionSplit() local
1601 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC); in tryInstructionSplit()
1610 getNumAllocatableRegsForConstraints(MI, VirtReg.reg, SuperRC, TII, in tryInstructionSplit()
DTargetLoweringBase.cpp1277 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); in findRepresentativeClass() local
1279 if (SuperRC->getSize() <= BestRC->getSize()) in findRepresentativeClass()
1281 if (!isLegalRC(SuperRC)) in findRepresentativeClass()
1283 BestRC = SuperRC; in findRepresentativeClass()
DMachineVerifier.cpp1031 const TargetRegisterClass *SuperRC = in visitMachineOperand() local
1033 if (!SuperRC) { in visitMachineOperand()
1037 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonCopyToCombine.cpp590 const TargetRegisterClass *SuperRC = nullptr; in combine() local
592 SuperRC = &Hexagon::DoubleRegsRegClass; in combine()
596 SuperRC = &Hexagon::HvxWRRegClass; in combine()
602 unsigned DoubleRegDest = TRI->getMatchingSuperReg(LoRegDef, SubLo, SuperRC); in combine()
DHexagonRegisterInfo.cpp335 if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses()) in getHexagonSubRegIndex() local
336 return getHexagonSubRegIndex(*SuperRC, GenIdx); in getHexagonSubRegIndex()
/external/llvm/lib/Target/AMDGPU/
DSILoadStoreOptimizer.cpp229 const TargetRegisterClass *SuperRC in mergeRead2Pair() local
231 unsigned DestReg = MRI->createVirtualRegister(SuperRC); in mergeRead2Pair()
DSIInstrInfo.h47 const TargetRegisterClass *SuperRC,
53 const TargetRegisterClass *SuperRC,
DSILowerControlFlow.cpp604 const TargetRegisterClass *SuperRC = TRI->getPhysRegClass(VecReg); in computeIndirectRegAndOffset() local
606 int NumElts = SuperRC->getSize() / RC->getSize(); in computeIndirectRegAndOffset()
DSIInstrInfo.cpp1904 const TargetRegisterClass *SuperRC, in buildExtractSubReg() argument
1922 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC); in buildExtractSubReg()
1937 const TargetRegisterClass *SuperRC, in buildExtractSubRegOrImm() argument
1950 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC, in buildExtractSubRegOrImm()
DAMDGPUISelDAGToDAG.cpp208 const TargetRegisterClass *SuperRC = in getOperandRegClass() local
213 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC, in getOperandRegClass()
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DCodeGenRegisters.h404 CodeGenRegisterClass *SuperRC) { in addSuperRegClass() argument
405 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()
/external/llvm/utils/TableGen/
DCodeGenRegisters.h365 CodeGenRegisterClass *SuperRC) { in addSuperRegClass() argument
366 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()