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Searched refs:TEX_LOGICAL_SRC_MCS (Results 1 – 3 of 3) sorted by relevance

/external/mesa3d/src/intel/compiler/
Dbrw_eu_defines.h779 TEX_LOGICAL_SRC_MCS, enumerator
Dbrw_fs_nir.cpp4662 srcs[TEX_LOGICAL_SRC_MCS] = retype(src, BRW_REGISTER_TYPE_D); in nir_emit_texture()
4683 if (srcs[TEX_LOGICAL_SRC_MCS].file == BAD_FILE && in nir_emit_texture()
4688 srcs[TEX_LOGICAL_SRC_MCS] = in nir_emit_texture()
4693 srcs[TEX_LOGICAL_SRC_MCS] = brw_imm_ud(0u); in nir_emit_texture()
4749 if (srcs[TEX_LOGICAL_SRC_MCS].file == BRW_IMMEDIATE_VALUE) { in nir_emit_texture()
4753 bld.OR(tmp, srcs[TEX_LOGICAL_SRC_MCS], in nir_emit_texture()
4754 offset(srcs[TEX_LOGICAL_SRC_MCS], bld, 1)); in nir_emit_texture()
4757 bld.CMP(dst, srcs[TEX_LOGICAL_SRC_MCS], brw_imm_ud(0u), in nir_emit_texture()
Dbrw_fs.cpp731 else if (i == TEX_LOGICAL_SRC_MCS && opcode == SHADER_OPCODE_TXF_CMS_W_LOGICAL) in components_read()
4423 const fs_reg &mcs = inst->src[TEX_LOGICAL_SRC_MCS]; in lower_sampler_logical_send()
4932 inst->components_read(TEX_LOGICAL_SRC_MCS); in get_sampler_lowered_simd_width()