| /external/v8/src/mips/ |
| D | constants-mips.h | 538 TGEU = ((6U << 3) + 1), enumerator
1294 FunctionFieldToBitNumber(TGE) | FunctionFieldToBitNumber(TGEU) |
1845 case TGEU: in IsTrap()
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| D | disasm-mips.cc | 479 case TGEU: in PrintCode()
1437 case TGEU: in DecodeTypeRegisterSPECIAL()
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| D | assembler-mips.cc | 2413 Instr instr = SPECIAL | TGEU | rs.code() << kRsShift in tgeu()
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| D | simulator-mips.cc | 4040 case TGEU: in DecodeTypeRegisterSPECIAL()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 534 TGEU = ((6U << 3) + 1), enumerator
1340 FunctionFieldToBitNumber(TGE) | FunctionFieldToBitNumber(TGEU) |
1928 case TGEU: in IsTrap()
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| D | disasm-mips64.cc | 520 case TGEU: in PrintCode()
1672 case TGEU: in DecodeTypeRegisterSPECIAL()
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| D | assembler-mips64.cc | 2657 Instr instr = SPECIAL | TGEU | rs.code() << kRsShift in tgeu()
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| D | simulator-mips64.cc | 4077 case TGEU: in DecodeTypeRegisterSPECIAL()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsScheduleP5600.td | 72 TGEU, TLT, TLTI, TLTU, TNE, TNEI, TRAP,
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| D | MipsInstrInfo.td | 2160 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm10, II_TGEU>, TEQ_FM<0x31>,
2756 (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 663 {DBGFIELD("TGEU") 1, false, false, 3, 2, 1, 1, 0, 0}, // #388
1683 {DBGFIELD("TGEU") 1, false, false, 38, 3, 1, 1, 0, 0}, // #388
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| D | MipsGenAsmWriter.inc | 3774 268459561U, // TGEU
6405 38U, // TGEU
7041 // TEQ, TGE, TGEU, TLT, TLTU, TNE
9358 case Mips::TGEU:
9366 // (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0)
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| D | MipsGenMCCodeEmitter.inc | 2559 UINT64_C(49), // TGEU
5200 case Mips::TGEU:
10285 Feature_HasStdEnc | Feature_HasMips2 | Feature_NotInMicroMips | 0, // TGEU = 2546
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| D | MipsGenInstrInfo.inc | 2561 TGEU = 2546,
3045 TGEU = 388,
6606 …modeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2546 = TGEU
10266 { Mips::TGEU, Mips::TGEU, Mips::TGEU_MM },
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| D | MipsGenAsmMatcher.inc | 7554 …{ 9293 /* tgeu */, Mips::TGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasStdEn…
7557 …{ 9293 /* tgeu */, Mips::TGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Featu…
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| D | MipsGenDisassemblerTables.inc | 3008 /* 1068 */ MCD::OPC_Decode, 242, 19, 182, 1, // Opcode: TGEU
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 1670 1107319530U, // TGEU
3384 0U, // TGEU
5389 // (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0)
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| D | MipsGenDisassemblerTables.inc | 633 /* 896 */ MCD_OPC_Decode, 245, 12, 50, // Opcode: TGEU
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.td | 1806 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm10, II_TGEU>, TEQ_FM<0x31>, ISA_MIPS2;
2287 (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
|