Searched refs:TGSI_OPCODE_AND (Results 1 – 16 of 16) sorted by relevance
| /external/virglrenderer/src/gallium/auxiliary/tgsi/ |
| D | tgsi_info.c | 129 { 1, 2, 0, 0, 0, 0, COMP, "AND", TGSI_OPCODE_AND },
330 case TGSI_OPCODE_AND: in tgsi_opcode_infer_type()
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| D | tgsi_util.c | 215 case TGSI_OPCODE_AND: in tgsi_util_get_inst_usage_mask()
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| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_info.c | 131 case TGSI_OPCODE_AND: in tgsi_opcode_infer_type()
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| D | tgsi_exec.c | 5461 case TGSI_OPCODE_AND: in exec_instruction()
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| /external/virglrenderer/src/gallium/include/pipe/ |
| D | p_shader_tokens.h | 420 #define TGSI_OPCODE_AND 89 macro
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| /external/mesa3d/src/gallium/include/pipe/ |
| D | p_shader_tokens.h | 431 #define TGSI_OPCODE_AND 89 macro
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| /external/mesa3d/src/mesa/state_tracker/ |
| D | st_glsl_to_tgsi.cpp | 1572 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2); in visit_expression()
1578 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2); in visit_expression()
1582 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, temp1, temp2); in visit_expression()
1587 emit_asm(ir, TGSI_OPCODE_AND, result_dst, temp1, temp2); in visit_expression()
1721 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]); in visit_expression()
1758 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], st_src_reg_for_float(1.0)); in visit_expression()
1776 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], st_src_reg_for_int(1)); in visit_expression()
1894 emit_asm(ir, TGSI_OPCODE_AND, result_dst, op[0], op[1]); in visit_expression()
2190 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0], st_src_reg_for_int(1)); in visit_expression()
2214 emit_asm(ir, TGSI_OPCODE_AND, temp_dst, op[0], st_src_reg_for_int(1)); in visit_expression()
[all …]
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| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| D | lp_bld_tgsi_aos.c | 797 case TGSI_OPCODE_AND: in lp_emit_instruction_aos()
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| D | lp_bld_tgsi_action.c | 2408 bld_base->op_actions[TGSI_OPCODE_AND].emit = and_emit_cpu; in lp_set_default_actions_cpu()
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_shader_tgsi_alu.c | 716 bld_base->op_actions[TGSI_OPCODE_AND].emit = emit_and; in si_shader_context_init_alu()
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| /external/mesa3d/src/gallium/auxiliary/nir/ |
| D | tgsi_to_nir.c | 1546 [TGSI_OPCODE_AND] = nir_op_iand,
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| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_from_tgsi.cpp | 580 case TGSI_OPCODE_AND: in inferSrcType()
3221 case TGSI_OPCODE_AND: in handleInstruction()
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| /external/mesa3d/src/gallium/drivers/svga/ |
| D | svga_tgsi_vgpu10.c | 565 case TGSI_OPCODE_AND: in translate_opcode()
5446 case TGSI_OPCODE_AND: in emit_vgpu10_instruction()
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| D | svga_tgsi_insn.c | 2883 case TGSI_OPCODE_AND: in svga_emit_instruction()
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_shader.c | 10339 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
10536 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
10758 [TGSI_OPCODE_AND] = { ALU_OP2_AND_INT, tgsi_op2},
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| /external/virglrenderer/src/ |
| D | vrend_shader.c | 3562 case TGSI_OPCODE_AND: in iter_instruction()
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