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Searched refs:TIED_TO (Results 1 – 25 of 52) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h662 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0) in getOperandBias()
667 Desc.getOperandConstraint(6, MCOI::TIED_TO) == 0) in getOperandBias()
672 if (NumOps >= 4 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && in getOperandBias()
673 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1) in getOperandBias()
677 if (NumOps == 9 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && in getOperandBias()
678 (Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1 || in getOperandBias()
679 Desc.getOperandConstraint(8, MCOI::TIED_TO) == 1) && in getOperandBias()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h633 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0) in getOperandBias()
635 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && in getOperandBias()
636 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1) in getOperandBias()
640 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && in getOperandBias()
641 Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1) in getOperandBias()
645 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps - 2, MCOI::TIED_TO) == 0) in getOperandBias()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMCodeEmitter.cpp1062 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in emitDataProcessingInstruction()
1142 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in emitLoadStoreInstruction()
1213 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in emitMiscLoadStoreInstruction()
1604 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in emitVFPArithInstruction()
1876 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in emitNEON2RegInstruction()
1891 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in emitNEON3RegInstruction()
1894 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in emitNEON3RegInstruction()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenInstrInfo.inc4278 …D_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCO…
4323 … ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<…
4327 …ER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << …
4329 … ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCO…
4330 … ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCO…
4331 … ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRe…
4332 … ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRe…
4333 … ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRno…
4335 … ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCO…
4340 …ER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << …
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DTargetInstrInfoImpl.cpp85 MI->getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) { in commuteInstruction()
89 MI->getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) { in commuteInstruction()
DMachineInstr.cpp1029 MCID.getOperandConstraint(i, MCOI::TIED_TO) == (int)DefOpIdx) { in isRegTiedToUseOperand()
1081 int DefIdx = MCID.getOperandConstraint(UseOpIdx, MCOI::TIED_TO); in isRegTiedToDefOperand()
/external/swiftshader/third_party/LLVM/include/llvm/MC/
DMCInstrDesc.h29 TIED_TO = 0, // Must be allocated the same register as. enumerator
/external/llvm/include/llvm/MC/
DMCInstrDesc.h34 TIED_TO = 0, // Must be allocated the same register as. enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/
DMCInstrDesc.h34 TIED_TO = 0, // Must be allocated the same register as. enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/
DUtils.cpp127 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO); in constrainSelectedInstRegOperands()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86CodeEmitter.cpp162 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1; in determineREX()
719 if (NumOps > 1 && Desc->getOperandConstraint(1, MCOI::TIED_TO) != -1) in emitInstruction()
721 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1,MCOI::TIED_TO)== 0) in emitInstruction()
DX86GenInstrInfo.inc3923 …{ { -1, 0, 0, MCOI::OPERAND_UNKNOWN }, { -1, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_…
3936 …::OPERAND_REGISTER }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_…
3937 …::OPERAND_REGISTER }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_…
3938 …::OPERAND_REGISTER }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_…
3940 …::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_…
3941 …::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_…
3942 …::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_…
3944 …::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_…
3945 …::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_…
3946 …::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_…
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp634 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1; in DetermineREXPrefix()
852 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1) in EncodeInstruction()
854 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, MCOI::TIED_TO)== 0) in EncodeInstruction()
/external/llvm/lib/Target/SystemZ/
DSystemZShortenInst.cpp68 if (MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && in tieOpsIfNeeded()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenInstrInfo.inc5487 …D_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCO…
5513 …ch64::ZPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::P…
5519 …4::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::F…
5541 …ch64::ZPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCO…
5542 …ch64::ZPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::Z…
5546 …4::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::F…
5547 …}, { AArch64::FPR128RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
5557 …ch64::ZPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCO…
5558 …ch64::ZPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCO…
5564 …64::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::G…
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZShortenInst.cpp68 if (MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && in tieOpsIfNeeded()
DSystemZHazardRecognizer.cpp128 MID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in has4RegOps()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenInstrInfo.inc3720 …D_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCO…
3760 …::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA1…
3761 …::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA1…
3762 …::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA1…
3782 …::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR6…
3783 …::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR3…
3784 …::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR6…
3785 …::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR3…
3786 …::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCO…
3787 …::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR6…
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-exegesis/lib/
DMCInstrDescView.cpp34 MCInstrDesc.getOperandConstraint(OpIndex, llvm::MCOI::TIED_TO); in Instruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DTargetInstrInfo.cpp188 MI.getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) { in commuteInstructionImpl()
193 MI.getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) { in commuteInstructionImpl()
/external/llvm/lib/CodeGen/
DTargetInstrInfo.cpp158 MI.getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) { in commuteInstructionImpl()
163 MI.getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) { in commuteInstructionImpl()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenInstrInfo.inc16857 …D_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCO…
16896 …ER, 0 }, { X86::GR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
16897 …ER, 0 }, { X86::GR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
16910 …ER, 0 }, { X86::GR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
16911 …ER, 0 }, { X86::GR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
16921 …X86::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCO…
16922 …X86::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<M…
16923 …X86::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { X86::GR16R…
16925 …X86::GR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCO…
16926 …X86::GR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<M…
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DScheduleDAGFast.cpp254 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in CopyAndMoveSuccessors()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGRRList.cpp1029 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in TryUnfoldSU()
2806 if (MCID.getOperandConstraint(i+NumRes, MCOI::TIED_TO) != -1) { in canClobber()
3028 if (MCID.getOperandConstraint(j+NumRes, MCOI::TIED_TO) == -1) in AddPseudoTwoAddrDeps()
/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGRRList.cpp1013 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in CopyAndMoveSuccessors()
2679 if (MCID.getOperandConstraint(i+NumRes, MCOI::TIED_TO) != -1) { in canClobber()
2901 if (MCID.getOperandConstraint(j+NumRes, MCOI::TIED_TO) == -1) in AddPseudoTwoAddrDeps()

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