| /external/v8/src/mips/ |
| D | constants-mips.h | 540 TLTU = ((6U << 3) + 3), enumerator
1295 FunctionFieldToBitNumber(TLT) | FunctionFieldToBitNumber(TLTU) |
1847 case TLTU: in IsTrap()
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| D | disasm-mips.cc | 481 case TLTU: in PrintCode()
1443 case TLTU: in DecodeTypeRegisterSPECIAL()
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| D | assembler-mips.cc | 2430 SPECIAL | TLTU | rs.code() << kRsShift in tltu()
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| D | simulator-mips.cc | 4046 case TLTU: in DecodeTypeRegisterSPECIAL()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 536 TLTU = ((6U << 3) + 3), enumerator
1341 FunctionFieldToBitNumber(TLT) | FunctionFieldToBitNumber(TLTU) |
1930 case TLTU: in IsTrap()
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| D | disasm-mips64.cc | 522 case TLTU: in PrintCode()
1678 case TLTU: in DecodeTypeRegisterSPECIAL()
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| D | assembler-mips64.cc | 2674 SPECIAL | TLTU | rs.code() << kRsShift in tltu()
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| D | simulator-mips64.cc | 4083 case TLTU: in DecodeTypeRegisterSPECIAL()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsScheduleP5600.td | 72 TGEU, TLT, TLTI, TLTU, TNE, TNEI, TRAP,
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| D | MipsInstrInfo.td | 2164 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm10, II_TLTU>, TEQ_FM<0x33>,
2760 (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 666 {DBGFIELD("TLTU") 1, false, false, 3, 2, 1, 1, 0, 0}, // #391
1686 {DBGFIELD("TLTU") 1, false, false, 38, 3, 1, 1, 0, 0}, // #391
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| D | MipsGenAsmWriter.inc | 3805 268459677U, // TLTU
6436 38U, // TLTU
7041 // TEQ, TGE, TGEU, TLT, TLTU, TNE
9410 case Mips::TLTU:
9418 // (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0)
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| D | MipsGenMCCodeEmitter.inc | 2590 UINT64_C(51), // TLTU
5202 case Mips::TLTU:
10316 Feature_HasStdEnc | Feature_HasMips2 | Feature_NotInMicroMips | 0, // TLTU = 2577
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| D | MipsGenInstrInfo.inc | 2592 TLTU = 2577,
3048 TLTU = 391,
6637 …modeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2577 = TLTU
10279 { Mips::TLTU, Mips::TLTU, Mips::TLTU_MM },
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| D | MipsGenAsmMatcher.inc | 7590 …{ 9393 /* tltu */, Mips::TLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasStdEn…
7593 …{ 9393 /* tltu */, Mips::TLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Featu…
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| D | MipsGenDisassemblerTables.inc | 3014 /* 1098 */ MCD::OPC_Decode, 145, 20, 182, 1, // Opcode: TLTU
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 1685 1107319605U, // TLTU
3399 0U, // TLTU
5415 // (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0)
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| D | MipsGenDisassemblerTables.inc | 639 /* 920 */ MCD_OPC_Decode, 132, 13, 50, // Opcode: TLTU
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.td | 1808 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm10, II_TLTU>, TEQ_FM<0x33>, ISA_MIPS2;
2291 (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
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