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Searched refs:TRAINING_DBG_1_REG (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/drivers/ddr/marvell/a38x/
Dmv_ddr_regs.h257 #define TRAINING_DBG_1_REG 0x15c0 macro
Dddr3_training_leveling.c173 TRAINING_DBG_1_REG, 0, (u32)(1 << 31))); in ddr3_tip_dynamic_read_leveling()
546 TRAINING_DBG_1_REG, 0, (u32)(1 << 31))); in ddr3_tip_dynamic_per_bit_read_leveling()