Searched refs:TRAINING_REG (Results 1 – 2 of 2) sorted by relevance
| /external/u-boot/drivers/ddr/marvell/a38x/ |
| D | ddr3_training_leveling.c | 194 TRAINING_REG, (1 << 24) | (1 << 20), in ddr3_tip_dynamic_read_leveling()
198 TRAINING_REG, (u32)(1 << 31), (u32)(1 << 31))); in ddr3_tip_dynamic_read_leveling()
362 TRAINING_REG, (0x80000008 | cs_mask), in ddr3_tip_legacy_dynamic_write_leveling()
367 (u32)0x80000000, TRAINING_REG, in ddr3_tip_legacy_dynamic_write_leveling()
400 (dev_num, ACCESS_TYPE_MULTICAST, 0, TRAINING_REG, in ddr3_tip_legacy_dynamic_read_leveling()
408 (u32)0x80000000, TRAINING_REG, in ddr3_tip_legacy_dynamic_read_leveling()
567 TRAINING_REG, (1 << 24) | (1 << 20), in ddr3_tip_dynamic_per_bit_read_leveling()
571 TRAINING_REG, (u32)(1 << 31), (u32)(1 << 31))); in ddr3_tip_dynamic_per_bit_read_leveling()
1730 ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, TRAINING_REG, in mv_ddr_rl_dqs_burst()
1735 ddr3_tip_if_write(0, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, TRAINING_REG, in mv_ddr_rl_dqs_burst()
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| D | mv_ddr_regs.h | 238 #define TRAINING_REG 0x15b0 macro
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