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Searched refs:TRAINING_SW_2_REG (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_training_leveling.c190 TRAINING_SW_2_REG, 0x1, 0x9)); in ddr3_tip_dynamic_read_leveling()
271 TRAINING_SW_2_REG, (1 << 3), (1 << 3))); in ddr3_tip_dynamic_read_leveling()
563 TRAINING_SW_2_REG, 0x1, 0x9)); in ddr3_tip_dynamic_per_bit_read_leveling()
751 TRAINING_SW_2_REG, (1 << 3), (1 << 3))); in ddr3_tip_dynamic_per_bit_read_leveling()
1051 TRAINING_SW_2_REG, 0x5, 0x7)); in ddr3_tip_dynamic_write_leveling()
1056 TRAINING_SW_2_REG, 0x4, 0x7)); in ddr3_tip_dynamic_write_leveling()
1496 TRAINING_SW_2_REG, 0x1, 0x5)); in ddr3_tip_dynamic_write_leveling_seq()
1721 ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, TRAINING_SW_2_REG, in mv_ddr_rl_dqs_burst()
1728 ddr3_tip_if_write(0, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, TRAINING_SW_2_REG, in mv_ddr_rl_dqs_burst()
Dmv_ddr_regs.h246 #define TRAINING_SW_2_REG 0x15b8 macro
Dddr3_training.c922 TRAINING_SW_2_REG, 0x100, 0x100)); in ddr3_pre_algo_config()
930 TRAINING_SW_2_REG, 0x0, 0x2)); in ddr3_pre_algo_config()
954 TRAINING_SW_2_REG, 0x0, 0x100)); in ddr3_post_algo_config()
1977 if_id, TRAINING_SW_2_REG, in ddr3_tip_reset_fifo_ptr()
1992 if_id, TRAINING_SW_2_REG, in ddr3_tip_reset_fifo_ptr()