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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dftrunc.ll13 ; EG: TRUNC
22 ; EG: TRUNC
23 ; EG: TRUNC
33 ; FIXME-EG: TRUNC
34 ; FIXME-EG: TRUNC
35 ; FIXME-EG: TRUNC
46 ; EG: TRUNC
47 ; EG: TRUNC
48 ; EG: TRUNC
49 ; EG: TRUNC
[all …]
Dllvm.round.ll9 ; GCN-DAG: v_trunc_f32_e32 [[TRUNC:v[0-9]+]], [[SX]]
10 ; GCN-DAG: v_sub_f32_e32 [[SUB:v[0-9]+]], [[SX]], [[TRUNC]]
15 ; GCN: v_add_f32_e32 [[RESULT:v[0-9]+]], [[TRUNC]], [[SEL]]
18 ; R600: TRUNC {{.*}}, [[ARG:KC[0-9]\[[0-9]+\]\.[XYZW]]]
69 ; GFX89: v_trunc_f16_e32 [[TRUNC:v[0-9]+]], [[SX]]
70 ; GFX89: v_sub_f16_e32 [[SUB:v[0-9]+]], [[SX]], [[TRUNC]]
73 ; GFX89: v_add_f16_e32 [[RESULT:v[0-9]+]], [[TRUNC]], [[SEL]]
/external/llvm/test/CodeGen/AMDGPU/
Dftrunc.ll13 ; EG: TRUNC
22 ; EG: TRUNC
23 ; EG: TRUNC
33 ; FIXME-EG: TRUNC
34 ; FIXME-EG: TRUNC
35 ; FIXME-EG: TRUNC
46 ; EG: TRUNC
47 ; EG: TRUNC
48 ; EG: TRUNC
49 ; EG: TRUNC
[all …]
Dllvm.round.ll8 ; SI-DAG: v_trunc_f32_e32 [[TRUNC:v[0-9]+]], [[SX]]
9 ; SI-DAG: v_sub_f32_e32 [[SUB:v[0-9]+]], [[SX]], [[TRUNC]]
14 ; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], [[SEL]], [[TRUNC]]
17 ; R600: TRUNC {{.*}}, [[ARG:KC[0-9]\[[0-9]+\]\.[XYZW]]]
Dudiv.ll97 ; SI: v_and_b32_e32 [[TRUNC:v[0-9]+]], 0xff, v{{[0-9]+}}
98 ; SI: buffer_store_dword [[TRUNC]]
111 ; SI: v_and_b32_e32 [[TRUNC:v[0-9]+]], 0xffff, v{{[0-9]+}}
112 ; SI: buffer_store_dword [[TRUNC]]
125 ; SI: v_and_b32_e32 [[TRUNC:v[0-9]+]], 0x7fffff, v{{[0-9]+}}
126 ; SI: buffer_store_dword [[TRUNC]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/GlobalISel/
Dx86_64-irtranslator.ll9 ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
10 ; CHECK: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[TRUNC]](s1)
22 ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
23 ; CHECK: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[TRUNC]](s1)
35 ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
36 ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s1)
48 ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
49 ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s1)
61 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
62 ; CHECK: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[TRUNC]](s8)
[all …]
Dlegalize-add.mir31 ; X64: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
33 ; X64: [[ADD:%[0-9]+]]:_(s8) = G_ADD [[TRUNC]], [[TRUNC1]]
39 ; X32: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
41 ; X32: [[ADD:%[0-9]+]]:_(s8) = G_ADD [[TRUNC]], [[TRUNC1]]
105 ; X32: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s8)
106 ; X32: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV]], [[UV2]], [[TRUNC]]
Dlegalize-trunc.mir23 ; X32: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
24 ; X32: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
35 ; X64: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
36 ; X64: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
Dlegalize-ext.mir109 ; X32: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
110 ; X32: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
116 ; X64: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
117 ; X64: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
142 ; X32: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
143 ; X32: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
149 ; X64: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
150 ; X64: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
456 ; X32: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
457 ; X32: $al = COPY [[TRUNC]](s8)
[all …]
Dlegalize-fmul-scalar.mir38 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
41 ; CHECK: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[TRUNC]], [[TRUNC1]]
77 ; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128)
80 ; CHECK: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[TRUNC]], [[TRUNC1]]
Dlegalize-fadd-scalar.mir38 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
41 ; CHECK: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[TRUNC]], [[TRUNC1]]
77 ; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128)
80 ; CHECK: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[TRUNC]], [[TRUNC1]]
Dlegalize-fdiv-scalar.mir38 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
41 ; CHECK: [[FDIV:%[0-9]+]]:_(s32) = G_FDIV [[TRUNC]], [[TRUNC1]]
77 ; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128)
80 ; CHECK: [[FDIV:%[0-9]+]]:_(s64) = G_FDIV [[TRUNC]], [[TRUNC1]]
Dlegalize-fsub-scalar.mir38 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
41 ; CHECK: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[TRUNC]], [[TRUNC1]]
77 ; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128)
80 ; CHECK: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[TRUNC]], [[TRUNC1]]
Dx86-legalize-sdiv.mir42 ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
45 ; CHECK: [[SDIV:%[0-9]+]]:_(s8) = G_SDIV [[TRUNC]], [[TRUNC1]]
74 ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
77 ; CHECK: [[SDIV:%[0-9]+]]:_(s16) = G_SDIV [[TRUNC]], [[TRUNC1]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dtrunc.ll245 ; CHECK-NEXT: [[TRUNC:%.*]] = shl i32 [[VAL_TR]], 31
246 ; CHECK-NEXT: ret i32 [[TRUNC]]
256 ; CHECK-NEXT: [[TRUNC:%.*]] = shl i32 [[VAL_TR]], 31
257 ; CHECK-NEXT: ret i32 [[TRUNC]]
267 ; CHECK-NEXT: [[TRUNC:%.*]] = shl i32 [[VAL_TR]], 31
268 ; CHECK-NEXT: ret i32 [[TRUNC]]
278 ; CHECK-NEXT: [[TRUNC:%.*]] = shl i32 [[VAL_TR]], 31
279 ; CHECK-NEXT: ret i32 [[TRUNC]]
289 ; CHECK-NEXT: [[TRUNC:%.*]] = shl i16 [[VAL_TR]], 15
290 ; CHECK-NEXT: ret i16 [[TRUNC]]
[all …]
Dnarrow.ll27 ; CHECK-NEXT: [[TRUNC:%.*]] = xor i32 [[TMP1]], 1
28 ; CHECK-NEXT: ret i32 [[TRUNC]]
40 ; CHECK-NEXT: [[TRUNC:%.*]] = xor <2 x i32> [[TMP1]], <i32 2, i32 2>
41 ; CHECK-NEXT: ret <2 x i32> [[TRUNC]]
53 ; CHECK-NEXT: [[TRUNC:%.*]] = or i3 [[TMP1]], 1
54 ; CHECK-NEXT: ret i3 [[TRUNC]]
66 ; CHECK-NEXT: [[TRUNC:%.*]] = or <2 x i8> [[TMP1]], <i8 -1, i8 0>
67 ; CHECK-NEXT: ret <2 x i8> [[TRUNC]]
79 ; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[AND]] to i31
80 ; CHECK-NEXT: ret i31 [[TRUNC]]
[all …]
Dfpcast.ll72 ; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc <1 x double> [[FREM]] to <1 x float>
73 ; CHECK-NEXT: ret <1 x float> [[TRUNC]]
83 ; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc double [[FREM]] to float
84 ; CHECK-NEXT: ret float [[TRUNC]]
95 ; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc double [[FREM]] to float
96 ; CHECK-NEXT: ret float [[TRUNC]]
Dselect-bitext.ll88 ; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 %a to i16
89 ; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[TRUNC]] to i64
101 ; CHECK-NEXT: [[TRUNC:%.*]] = zext <2 x i32> %a to <2 x i64>
102 ; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i64> [[TRUNC]], <i64 48, i64 48>
115 ; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 %a to i16
116 ; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[TRUNC]] to i32
128 ; CHECK-NEXT: [[TRUNC:%.*]] = trunc <2 x i64> %a to <2 x i32>
129 ; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i32> [[TRUNC]], <i32 16, i32 16>
207 ; CHECK-NEXT: [[TRUNC:%.*]] = trunc <2 x i64> %a to <2 x i32>
208 ; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[TRUNC]], <i32 65535, i32 65535>
[all …]
/external/freetype/src/smooth/
Dftgrays.c332 #undef TRUNC
336 #define TRUNC( x ) ( (TCoord)( (x) >> PIXEL_BITS ) ) macro
615 ex1 = TRUNC( x1 ); in gray_render_scanline()
616 ex2 = TRUNC( x2 ); in gray_render_scanline()
710 ey1 = TRUNC( ras.y ); in gray_render_line()
711 ey2 = TRUNC( to_y ); /* if (ey2 >= ras.max_ey) ey2 = ras.max_ey-1; */ in gray_render_line()
734 TCoord ex = TRUNC( ras.x ); in gray_render_line()
796 gray_set_cell( RAS_VAR_ TRUNC( x ), ey1 ); in gray_render_line()
823 gray_set_cell( RAS_VAR_ TRUNC( x ), ey1 ); in gray_render_line()
850 ey1 = TRUNC( ras.y ); in gray_render_line()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/GlobalISel/
Dlegalize-rem.mir64 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
66 ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[TRUNC]], [[TRUNC1]]
68 ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[MUL]]
95 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
96 ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]]
142 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
145 ; CHECK: $s0 = COPY [[TRUNC]](s32)
Dlegalize-simple.mir49 ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)
54 ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
58 ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC2]], [[TRUNC3]]
63 ; CHECK: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC4]], [[TRUNC5]]
68 ; CHECK: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC6]], [[TRUNC7]]
71 ; CHECK: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC1]], [[TRUNC1]]
72 ; CHECK: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY]]
/external/llvm/test/Transforms/IndVarSimplify/
Dpr25578.ll14 ; CHECK: %[[TRUNC:.*]] = trunc i64 %[[INDVAR]] to i32
38 ; CHECK: %i_lcssa = phi i32 [ %[[TRUNC]], %L2_exiting_1 ], [ %[[TRUNC]], %L2_exiting_2 ]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/IndVarSimplify/
Dpr25578.ll16 ; CHECK: %[[TRUNC:.*]] = trunc i64 %[[INDVAR]] to i32
41 ; CHECK: %i_lcssa = phi i32 [ %[[TRUNC]], %L2_exiting_1 ], [ %[[TRUNC]], %L2_exiting_2 ]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SimplifyCFG/X86/
Dspeculate-cttz-ctlz.ll155 ; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i64 [[CTTZ]] to i32
156 ; BMI-NEXT: select i1 [[COND]], i32 64, i32 [[TRUNC]]
201 ; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i64 [[CTLZ]] to i32
202 ; LZCNT-NEXT: select i1 [[COND]], i32 64, i32 [[TRUNC]]
224 ; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i64 [[CTLZ]] to i16
225 ; LZCNT-NEXT: select i1 [[COND]], i16 64, i16 [[TRUNC]]
247 ; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i32 [[CTLZ]] to i16
248 ; LZCNT-NEXT: select i1 [[COND]], i16 32, i16 [[TRUNC]]
270 ; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i64 [[CTTZ]] to i16
271 ; BMI-NEXT: select i1 [[COND]], i16 64, i16 [[TRUNC]]
[all …]
/external/llvm/test/Transforms/SimplifyCFG/X86/
Dspeculate-cttz-ctlz.ll155 ; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i64 [[CTTZ]] to i32
156 ; BMI-NEXT: select i1 [[COND]], i32 64, i32 [[TRUNC]]
201 ; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i64 [[CTLZ]] to i32
202 ; LZCNT-NEXT: select i1 [[COND]], i32 64, i32 [[TRUNC]]
224 ; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i64 [[CTLZ]] to i16
225 ; LZCNT-NEXT: select i1 [[COND]], i16 64, i16 [[TRUNC]]
247 ; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i32 [[CTLZ]] to i16
248 ; LZCNT-NEXT: select i1 [[COND]], i16 32, i16 [[TRUNC]]
270 ; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i64 [[CTTZ]] to i16
271 ; BMI-NEXT: select i1 [[COND]], i16 64, i16 [[TRUNC]]
[all …]

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