| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_inlines.h | 69 case TYPE_U64: in typeSizeof()
93 case TYPE_U64: in typeSizeofLog2()
112 case 8: return flt ? TYPE_F64 : (sgn ? TYPE_S64 : TYPE_U64);
139 case TYPE_U64: in isSignedType()
151 case TYPE_U64: return TYPE_S64; in intTypeToSigned()
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| D | nv50_ir_from_tgsi.cpp | 677 return nv50_ir::TYPE_U64; in inferSrcType()
739 return nv50_ir::TYPE_U64; in inferDstType()
3929 mkOp2(OP_MERGE, TYPE_U64, dreg, src0, src1); in handleInstruction()
3974 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]); in handleInstruction()
3988 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]); in handleInstruction()
4000 mkOp2(OP_MERGE, TYPE_U64, src0, srcComp[0], srcComp[1]); in handleInstruction()
4023 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]); in handleInstruction()
4035 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]); in handleInstruction()
4060 mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]); in handleInstruction()
4063 mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]); in handleInstruction()
[all …]
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| D | nv50_ir_build_util.cpp | 378 imm->reg.type = TYPE_U64; in mkImm()
422 return mkOp1v(OP_MOV, TYPE_U64, dst ? dst : getScratch(8), mkImm(u)); in loadImm()
568 case TYPE_U64: hTy = TYPE_U32; break; in split64BitOpPostRA()
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| D | nv50_ir_lowering_nvc0.cpp | 112 bld.mkOp2(OP_MERGE, TYPE_U64, def, dst[0], dst[1]); in handleRCPRSQ()
225 bld.mkOp2(OP_MERGE, TYPE_U64, dst64, dst[0], dst[1]); in handleShift()
254 bld.mkOp2(OP_MERGE, TYPE_U64, dst64, dst[0], dst[1]); in handleShift()
1568 base = bld.mkOp2v(OP_ADD, TYPE_U64, base, base, ptr); in handleATOM()
1638 bld.mkOp2(OP_MERGE, TYPE_U64, dreg, cas->getSrc(1), cas->getSrc(2)); in handleCasExch()
1666 mkLoadv(TYPE_U64, bld.mkSymbol(FILE_MEMORY_CONST, b, TYPE_U64, off), ptr); in loadResInfo64()
1679 mkLoadv(TYPE_U32, bld.mkSymbol(FILE_MEMORY_CONST, b, TYPE_U64, off + 8), ptr); in loadResLength32()
2028 bld.mkOp2(OP_MERGE, TYPE_U64, addr, bf, eau); in processSurfaceCoordsNVE4()
2031 bld.mkOp2(OP_ADD, TYPE_U64, addr, addr, off); in processSurfaceCoordsNVE4()
2311 su->dType = TYPE_U64; in handleSurfaceOpNVC0()
[all …]
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| D | nv50_ir_emit_gm107.cpp | 2135 case TYPE_U64: in emitSHF()
2513 case TYPE_U64: dType = 1; break; in emitATOM()
2523 case TYPE_U64: dType = 2; break; in emitATOM()
2553 case TYPE_U64: dType = 1; break; in emitATOMS()
2564 case TYPE_U64: dType = 2; break; in emitATOMS()
2592 case TYPE_U64: dType = 2; break; in emitRED()
3060 case TYPE_U64: type = 5; break; in emitSULDx()
3092 case TYPE_U64: type = 2; break; in emitSUREDx()
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| D | nv50_ir_emit_nv50.cpp | 591 case TYPE_U64: enc = 0x4; break; in emitLoadStoreSizeLG()
1370 case TYPE_U64: code[1] = 0x44404000; break; in emitCVT()
1388 case TYPE_U64: in emitCVT()
1401 case TYPE_U64: code[1] = 0x40404000; break; in emitCVT()
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| D | nv50_ir_print.cpp | 464 case TYPE_U64: in print()
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| D | nv50_ir_lowering_nv50.cpp | 53 case TYPE_S64: fTy = TYPE_U64; break; in expandIntegerMUL()
60 case TYPE_U64: hTy = TYPE_U32; break; in expandIntegerMUL()
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| D | nv50_ir.h | 268 TYPE_U64, // 64 bit operations are only lowered after register allocation enumerator
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| D | nv50_ir_emit_gk110.cpp | 2119 case TYPE_U64: in emitLoadStoreType()
2400 case TYPE_U64: code[1] |= 0x00200000; break; in emitATOM()
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| D | nv50_ir.cpp | 397 case TYPE_U64: in isInteger()
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| D | nv50_ir_emit_nvc0.cpp | 1807 case TYPE_U64: in emitLoadStoreType()
2091 if (i->dType == TYPE_U64) { in emitATOM()
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| D | nv50_ir_peephole.cpp | 680 case TYPE_U64: in expr()
2332 case TYPE_U64: hTy = TYPE_U32; break; in visit()
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| /external/ltp/utils/ffsb-6.0-rc2/ |
| D | parser.h | 30 #define TYPE_U64 0x0002 macro
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| D | parser.c | 332 case TYPE_U64: in set_option()
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| /external/deqp/external/vulkancts/modules/vulkan/spirv_assembly/ |
| D | vktSpvAsmTypeTests.cpp | 125 TYPE_U64, enumerator
489 return (isSigned) ? TYPE_I64 : TYPE_U64; in getInputType()
2656 …testCtx, "u64", "uint64 tests", "shaderInt64", "Int64", "OpTypeInt 64 0", TYPE_U64, 64, vectorSize) in SpvAsmTypeUint64Tests()
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