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Searched refs:TargetOpcode (Results 1 – 25 of 387) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp79 case TargetOpcode::G_SDIV: in getRTLibDesc()
82 case TargetOpcode::G_UDIV: in getRTLibDesc()
85 case TargetOpcode::G_SREM: in getRTLibDesc()
88 case TargetOpcode::G_UREM: in getRTLibDesc()
91 case TargetOpcode::G_FADD: in getRTLibDesc()
94 case TargetOpcode::G_FSUB: in getRTLibDesc()
97 case TargetOpcode::G_FMUL: in getRTLibDesc()
100 case TargetOpcode::G_FDIV: in getRTLibDesc()
103 case TargetOpcode::G_FREM: in getRTLibDesc()
105 case TargetOpcode::G_FPOW: in getRTLibDesc()
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DMachineIRBuilder.cpp98 getTII().get(TargetOpcode::DBG_VALUE), in buildDirectDbgValue()
110 getTII().get(TargetOpcode::DBG_VALUE), in buildIndirectDbgValue()
122 return buildInstr(TargetOpcode::DBG_VALUE) in buildFIDbgValue()
136 auto MIB = buildInstr(TargetOpcode::DBG_VALUE); in buildConstDbgValue()
155 return buildInstr(TargetOpcode::G_FRAME_INDEX) in buildFrameIndex()
167 return buildInstr(TargetOpcode::G_GLOBAL_VALUE) in buildGlobalValue()
187 return buildInstr(TargetOpcode::G_GEP) in buildGEP()
217 return buildInstr(TargetOpcode::G_PTR_MASK) in buildPtrMask()
224 return buildInstr(TargetOpcode::G_BR).addMBB(&Dest); in buildBr()
229 return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt); in buildBrIndirect()
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DLegalizerInfo.cpp113 setScalarAction(TargetOpcode::G_ANYEXT, 1, {{1, Legal}}); in LegalizerInfo()
114 setScalarAction(TargetOpcode::G_ZEXT, 1, {{1, Legal}}); in LegalizerInfo()
115 setScalarAction(TargetOpcode::G_SEXT, 1, {{1, Legal}}); in LegalizerInfo()
116 setScalarAction(TargetOpcode::G_TRUNC, 0, {{1, Legal}}); in LegalizerInfo()
117 setScalarAction(TargetOpcode::G_TRUNC, 1, {{1, Legal}}); in LegalizerInfo()
119 setScalarAction(TargetOpcode::G_INTRINSIC, 0, {{1, Legal}}); in LegalizerInfo()
120 setScalarAction(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, 0, {{1, Legal}}); in LegalizerInfo()
123 TargetOpcode::G_IMPLICIT_DEF, 0, narrowToSmallerAndUnsupportedIfTooSmall); in LegalizerInfo()
125 TargetOpcode::G_ADD, 0, widenToLargerTypesAndNarrowToLargest); in LegalizerInfo()
127 TargetOpcode::G_OR, 0, widenToLargerTypesAndNarrowToLargest); in LegalizerInfo()
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DLegalizer.cpp61 case TargetOpcode::G_TRUNC: in isArtifact()
62 case TargetOpcode::G_ZEXT: in isArtifact()
63 case TargetOpcode::G_ANYEXT: in isArtifact()
64 case TargetOpcode::G_SEXT: in isArtifact()
65 case TargetOpcode::G_MERGE_VALUES: in isArtifact()
66 case TargetOpcode::G_UNMERGE_VALUES: in isArtifact()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/
DConstantFoldingMIRBuilder.h30 case TargetOpcode::G_ADD: in ConstantFoldBinOp()
32 case TargetOpcode::G_AND: in ConstantFoldBinOp()
34 case TargetOpcode::G_ASHR: in ConstantFoldBinOp()
36 case TargetOpcode::G_LSHR: in ConstantFoldBinOp()
38 case TargetOpcode::G_MUL: in ConstantFoldBinOp()
40 case TargetOpcode::G_OR: in ConstantFoldBinOp()
42 case TargetOpcode::G_SHL: in ConstantFoldBinOp()
44 case TargetOpcode::G_SUB: in ConstantFoldBinOp()
46 case TargetOpcode::G_XOR: in ConstantFoldBinOp()
48 case TargetOpcode::G_UDIV: in ConstantFoldBinOp()
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DMIPatternMatch.h195 inline BinaryOp_match<LHS, RHS, TargetOpcode::G_ADD, true>
197 return BinaryOp_match<LHS, RHS, TargetOpcode::G_ADD, true>(L, R);
201 inline BinaryOp_match<LHS, RHS, TargetOpcode::G_SUB> m_GSub(const LHS &L,
203 return BinaryOp_match<LHS, RHS, TargetOpcode::G_SUB>(L, R);
207 inline BinaryOp_match<LHS, RHS, TargetOpcode::G_MUL, true>
209 return BinaryOp_match<LHS, RHS, TargetOpcode::G_MUL, true>(L, R);
213 inline BinaryOp_match<LHS, RHS, TargetOpcode::G_FADD, true>
215 return BinaryOp_match<LHS, RHS, TargetOpcode::G_FADD, true>(L, R);
219 inline BinaryOp_match<LHS, RHS, TargetOpcode::G_FMUL, true>
221 return BinaryOp_match<LHS, RHS, TargetOpcode::G_FMUL, true>(L, R);
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DLegalizationArtifactCombiner.h37 if (MI.getOpcode() != TargetOpcode::G_ANYEXT) in tryCombineAnyExt()
39 if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_TRUNC, in tryCombineAnyExt()
56 if (MI.getOpcode() != TargetOpcode::G_ZEXT) in tryCombineZExt()
58 if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_TRUNC, in tryCombineZExt()
62 if (isInstUnsupported({TargetOpcode::G_AND, {DstTy}}) || in tryCombineZExt()
63 isInstUnsupported({TargetOpcode::G_CONSTANT, {DstTy}})) in tryCombineZExt()
84 if (MI.getOpcode() != TargetOpcode::G_SEXT) in tryCombineSExt()
86 if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_TRUNC, in tryCombineSExt()
90 if (isInstUnsupported({TargetOpcode::G_SHL, {DstTy}}) || in tryCombineSExt()
91 isInstUnsupported({TargetOpcode::G_ASHR, {DstTy}}) || in tryCombineSExt()
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DIRTranslator.h304 return translateBinaryOp(TargetOpcode::G_ADD, U, MIRBuilder); in translateAdd()
307 return translateBinaryOp(TargetOpcode::G_SUB, U, MIRBuilder); in translateSub()
310 return translateBinaryOp(TargetOpcode::G_AND, U, MIRBuilder); in translateAnd()
313 return translateBinaryOp(TargetOpcode::G_MUL, U, MIRBuilder); in translateMul()
316 return translateBinaryOp(TargetOpcode::G_OR, U, MIRBuilder); in translateOr()
319 return translateBinaryOp(TargetOpcode::G_XOR, U, MIRBuilder); in translateXor()
323 return translateBinaryOp(TargetOpcode::G_UDIV, U, MIRBuilder); in translateUDiv()
326 return translateBinaryOp(TargetOpcode::G_SDIV, U, MIRBuilder); in translateSDiv()
329 return translateBinaryOp(TargetOpcode::G_UREM, U, MIRBuilder); in translateURem()
332 return translateBinaryOp(TargetOpcode::G_SREM, U, MIRBuilder); in translateSRem()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64RegisterBankInfo.cpp272 case TargetOpcode::G_OR: { in getInstrAlternativeMappings()
295 case TargetOpcode::G_BITCAST: { in getInstrAlternativeMappings()
331 case TargetOpcode::G_LOAD: { in getInstrAlternativeMappings()
368 case TargetOpcode::G_OR: in applyMappingImpl()
369 case TargetOpcode::G_BITCAST: in applyMappingImpl()
370 case TargetOpcode::G_LOAD: in applyMappingImpl()
385 case TargetOpcode::G_FADD: in isPreISelGenericFloatingPointOpcode()
386 case TargetOpcode::G_FSUB: in isPreISelGenericFloatingPointOpcode()
387 case TargetOpcode::G_FMUL: in isPreISelGenericFloatingPointOpcode()
388 case TargetOpcode::G_FDIV: in isPreISelGenericFloatingPointOpcode()
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DAArch64InstructionSelector.cpp228 case TargetOpcode::G_SHL: in selectBinaryOp()
230 case TargetOpcode::G_LSHR: in selectBinaryOp()
232 case TargetOpcode::G_ASHR: in selectBinaryOp()
239 case TargetOpcode::G_GEP: in selectBinaryOp()
241 case TargetOpcode::G_SHL: in selectBinaryOp()
243 case TargetOpcode::G_LSHR: in selectBinaryOp()
245 case TargetOpcode::G_ASHR: in selectBinaryOp()
256 case TargetOpcode::G_FADD: in selectBinaryOp()
258 case TargetOpcode::G_FSUB: in selectBinaryOp()
260 case TargetOpcode::G_FMUL: in selectBinaryOp()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86RegisterBankInfo.cpp167 if (!isPreISelGenericOpcode(Opc) || Opc == TargetOpcode::G_PHI) { in getInstrMapping()
174 case TargetOpcode::G_ADD: in getInstrMapping()
175 case TargetOpcode::G_SUB: in getInstrMapping()
176 case TargetOpcode::G_MUL: in getInstrMapping()
177 case TargetOpcode::G_SHL: in getInstrMapping()
178 case TargetOpcode::G_LSHR: in getInstrMapping()
179 case TargetOpcode::G_ASHR: in getInstrMapping()
182 case TargetOpcode::G_FADD: in getInstrMapping()
183 case TargetOpcode::G_FSUB: in getInstrMapping()
184 case TargetOpcode::G_FMUL: in getInstrMapping()
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DX86InstructionSelector.cpp255 TII.get(TargetOpcode::SUBREG_TO_REG)) in selectCopy()
321 if (Opcode == TargetOpcode::LOAD_STACK_GUARD) in select()
342 case TargetOpcode::G_STORE: in select()
343 case TargetOpcode::G_LOAD: in select()
345 case TargetOpcode::G_GEP: in select()
346 case TargetOpcode::G_FRAME_INDEX: in select()
348 case TargetOpcode::G_GLOBAL_VALUE: in select()
350 case TargetOpcode::G_CONSTANT: in select()
352 case TargetOpcode::G_FCONSTANT: in select()
354 case TargetOpcode::G_PTRTOINT: in select()
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DMachineInstr.h831 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
832 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
834 return getOpcode() == TargetOpcode::ANNOTATION_LABEL;
843 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
849 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
850 bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
862 return getOpcode() == TargetOpcode::PHI ||
863 getOpcode() == TargetOpcode::G_PHI;
865 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
866 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
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DTargetOpcodes.h21 namespace TargetOpcode {
32 return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_START && in isPreISelGenericOpcode()
33 Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; in isPreISelGenericOpcode()
38 return Opcode > TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; in isTargetSpecificOpcode()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DPatchableFunction.cpp46 case TargetOpcode::IMPLICIT_DEF: in doesNotGeneratecode()
47 case TargetOpcode::KILL: in doesNotGeneratecode()
48 case TargetOpcode::CFI_INSTRUCTION: in doesNotGeneratecode()
49 case TargetOpcode::EH_LABEL: in doesNotGeneratecode()
50 case TargetOpcode::GC_LABEL: in doesNotGeneratecode()
51 case TargetOpcode::DBG_VALUE: in doesNotGeneratecode()
52 case TargetOpcode::DBG_LABEL: in doesNotGeneratecode()
74 TII->get(TargetOpcode::PATCHABLE_OP)) in runOnMachineFunction()
DExpandPostRAPseudos.cpp99 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
110 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
137 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
154 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
209 case TargetOpcode::SUBREG_TO_REG: in runOnMachineFunction()
212 case TargetOpcode::COPY: in runOnMachineFunction()
215 case TargetOpcode::DBG_VALUE: in runOnMachineFunction()
217 case TargetOpcode::INSERT_SUBREG: in runOnMachineFunction()
218 case TargetOpcode::EXTRACT_SUBREG: in runOnMachineFunction()
DDetectDeadLanes.cpp143 case TargetOpcode::COPY: in lowersToCopies()
144 case TargetOpcode::PHI: in lowersToCopies()
145 case TargetOpcode::INSERT_SUBREG: in lowersToCopies()
146 case TargetOpcode::REG_SEQUENCE: in lowersToCopies()
147 case TargetOpcode::EXTRACT_SUBREG: in lowersToCopies()
168 case TargetOpcode::INSERT_SUBREG: in isCrossCopy()
172 case TargetOpcode::REG_SEQUENCE: { in isCrossCopy()
177 case TargetOpcode::EXTRACT_SUBREG: { in isCrossCopy()
238 case TargetOpcode::COPY: in transferUsedLanes()
239 case TargetOpcode::PHI: in transferUsedLanes()
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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DMachineInstr.h258 return getOpcode() == TargetOpcode::PROLOG_LABEL ||
259 getOpcode() == TargetOpcode::EH_LABEL ||
260 getOpcode() == TargetOpcode::GC_LABEL;
264 return getOpcode() == TargetOpcode::PROLOG_LABEL;
266 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
267 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
268 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
270 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
271 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
272 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
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/external/llvm/lib/CodeGen/
DPatchableFunction.cpp46 case TargetOpcode::IMPLICIT_DEF: in doesNotGeneratecode()
47 case TargetOpcode::KILL: in doesNotGeneratecode()
48 case TargetOpcode::CFI_INSTRUCTION: in doesNotGeneratecode()
49 case TargetOpcode::EH_LABEL: in doesNotGeneratecode()
50 case TargetOpcode::GC_LABEL: in doesNotGeneratecode()
51 case TargetOpcode::DBG_VALUE: in doesNotGeneratecode()
73 TII->get(TargetOpcode::PATCHABLE_OP)) in runOnMachineFunction()
DDetectDeadLanes.cpp145 case TargetOpcode::COPY: in lowersToCopies()
146 case TargetOpcode::PHI: in lowersToCopies()
147 case TargetOpcode::INSERT_SUBREG: in lowersToCopies()
148 case TargetOpcode::REG_SEQUENCE: in lowersToCopies()
149 case TargetOpcode::EXTRACT_SUBREG: in lowersToCopies()
170 case TargetOpcode::INSERT_SUBREG: in isCrossCopy()
174 case TargetOpcode::REG_SEQUENCE: { in isCrossCopy()
179 case TargetOpcode::EXTRACT_SUBREG: { in isCrossCopy()
240 case TargetOpcode::COPY: in transferUsedLanes()
241 case TargetOpcode::PHI: in transferUsedLanes()
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DExpandPostRAPseudos.cpp103 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
114 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
141 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
156 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
211 case TargetOpcode::SUBREG_TO_REG: in runOnMachineFunction()
214 case TargetOpcode::COPY: in runOnMachineFunction()
217 case TargetOpcode::DBG_VALUE: in runOnMachineFunction()
219 case TargetOpcode::INSERT_SUBREG: in runOnMachineFunction()
220 case TargetOpcode::EXTRACT_SUBREG: in runOnMachineFunction()
/external/llvm/include/llvm/CodeGen/
DMachineInstr.h775 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
776 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
781 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
787 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
796 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
797 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
798 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
799 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
801 return getOpcode() == TargetOpcode::INLINEASM && getInlineAsmDialect();
806 return getOpcode() == TargetOpcode::INSERT_SUBREG;
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/external/llvm/lib/Target/Hexagon/
DHexagonMachineScheduler.cpp53 case TargetOpcode::EXTRACT_SUBREG: in isResourceAvailable()
54 case TargetOpcode::INSERT_SUBREG: in isResourceAvailable()
55 case TargetOpcode::SUBREG_TO_REG: in isResourceAvailable()
56 case TargetOpcode::REG_SEQUENCE: in isResourceAvailable()
57 case TargetOpcode::IMPLICIT_DEF: in isResourceAvailable()
58 case TargetOpcode::COPY: in isResourceAvailable()
59 case TargetOpcode::INLINEASM: in isResourceAvailable()
105 case TargetOpcode::EXTRACT_SUBREG: in reserveResources()
106 case TargetOpcode::INSERT_SUBREG: in reserveResources()
107 case TargetOpcode::SUBREG_TO_REG: in reserveResources()
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/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp177 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), in EmitCopyFromReg()
212 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && in CreateVirtualRegisters()
287 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { in getVR()
298 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); in getVR()
341 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); in AddRegisterOperand()
463 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg) in ConstrainForSubReg()
489 if (Opc == TargetOpcode::EXTRACT_SUBREG) { in EmitSubregNode()
511 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg); in EmitSubregNode()
527 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx); in EmitSubregNode()
529 } else if (Opc == TargetOpcode::INSERT_SUBREG || in EmitSubregNode()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp178 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), in EmitCopyFromReg()
213 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && in CreateVirtualRegisters()
287 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { in getVR()
298 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); in getVR()
345 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); in AddRegisterOperand()
409 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); in AddOperand()
486 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg) in ConstrainForSubReg()
512 if (Opc == TargetOpcode::EXTRACT_SUBREG) { in EmitSubregNode()
543 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg); in EmitSubregNode()
561 TII->get(TargetOpcode::COPY), VRBase); in EmitSubregNode()
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