| /external/swiftshader/third_party/LLVM/lib/MC/MCDisassembler/ |
| D | EDDisassembler.cpp | 163 Tgt = TargetRegistry::lookupTarget(tripleString, in EDDisassembler()
166 if (!Tgt) in EDDisassembler()
169 MRI.reset(Tgt->createMCRegInfo(tripleString)); in EDDisassembler()
176 AsmInfo.reset(Tgt->createMCAsmInfo(tripleString)); in EDDisassembler()
181 STI.reset(Tgt->createMCSubtargetInfo(tripleString, "", "")); in EDDisassembler()
186 Disassembler.reset(Tgt->createMCDisassembler(*STI)); in EDDisassembler()
195 InstPrinter.reset(Tgt->createMCInstPrinter(LLVMSyntaxVariant, *AsmInfo, *STI)); in EDDisassembler()
201 SpecificAsmLexer.reset(Tgt->createMCAsmLexer(*MRI, *AsmInfo)); in EDDisassembler()
380 OwningPtr<MCSubtargetInfo> STI(Tgt->createMCSubtargetInfo(triple, "", "")); in parseInst()
382 TargetParser(Tgt->createMCAsmParser(*STI, *genericParser)); in parseInst()
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| D | EDDisassembler.h | 137 const llvm::Target *Tgt; member
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/InstPrinter/ |
| D | AMDGPUInstPrinter.cpp | 804 uint32_t Tgt = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1); in printExpTgt() local
806 if (Tgt <= 7) in printExpTgt()
807 O << " mrt" << Tgt; in printExpTgt()
808 else if (Tgt == 8) in printExpTgt()
810 else if (Tgt == 9) in printExpTgt()
812 else if (Tgt >= 12 && Tgt <= 15) in printExpTgt()
813 O << " pos" << Tgt - 12; in printExpTgt()
814 else if (Tgt >= 32 && Tgt <= 63) in printExpTgt()
815 O << " param" << Tgt - 32; in printExpTgt()
818 O << " invalid_target_" << Tgt; in printExpTgt()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 218 buildEXP(const TargetInstrInfo &TII, MachineInstr *Insert, unsigned Tgt, in buildEXP() argument
225 .addImm(Tgt) in buildEXP()
245 int64_t Tgt = getConstant(MRI.getVRegDef(I.getOperand(1).getReg())); in selectG_INTRINSIC_W_SIDE_EFFECTS() local
250 MachineInstr *Exp = buildEXP(TII, &I, Tgt, I.getOperand(3).getReg(), in selectG_INTRINSIC_W_SIDE_EFFECTS()
261 int64_t Tgt = getConstant(MRI.getVRegDef(I.getOperand(1).getReg())); in selectG_INTRINSIC_W_SIDE_EFFECTS() local
270 MachineInstr *Exp = buildEXP(TII, &I, Tgt, Reg0, Reg1, Undef, Undef, VM, in selectG_INTRINSIC_W_SIDE_EFFECTS()
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| D | SIISelLowering.cpp | 5299 const ConstantSDNode *Tgt = cast<ConstantSDNode>(Op.getOperand(2)); in LowerINTRINSIC_VOID() local
5306 DAG.getTargetConstant(Tgt->getZExtValue(), DL, MVT::i8), // tgt in LowerINTRINSIC_VOID()
5321 const ConstantSDNode *Tgt = cast<ConstantSDNode>(Op.getOperand(2)); in LowerINTRINSIC_VOID() local
5331 DAG.getTargetConstant(Tgt->getZExtValue(), DL, MVT::i8), // tgt in LowerINTRINSIC_VOID()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsLongBranch.cpp | 153 MachineBasicBlock *Tgt = getTargetMBB(*FirstBr); in splitMBB() local
155 NewMBB->removeSuccessor(Tgt, true); in splitMBB()
157 MBB->addSuccessor(Tgt); in splitMBB()
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| D | MipsISelLowering.h | 330 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), in getAddrGlobal() local
332 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0); in getAddrGlobal()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsBranchExpansion.cpp | 269 MachineBasicBlock *Tgt = getTargetMBB(*FirstBr); in splitMBB() local
271 NewMBB->removeSuccessor(Tgt, true); in splitMBB()
273 MBB->addSuccessor(Tgt); in splitMBB()
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| D | MipsISelLowering.h | 409 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), in getAddrGlobal() local
411 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo); in getAddrGlobal()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 227 MachineInstrBuilder MachineIRBuilderBase::buildBrIndirect(unsigned Tgt) { in buildBrIndirect() argument
228 assert(getMRI()->getType(Tgt).isPointer() && "invalid branch destination"); in buildBrIndirect()
229 return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt); in buildBrIndirect()
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| D | IRTranslator.cpp | 411 const unsigned Tgt = getOrCreateVReg(*BrInst.getAddress()); in translateIndirectBr() local
412 MIRBuilder.buildBrIndirect(Tgt); in translateIndirectBr()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 451 MachineInstrBuilder buildBrIndirect(unsigned Tgt);
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| /external/eigen/Eigen/src/Core/ |
| D | GenericPacketMath.h | 122 template <typename Src, typename Tgt> struct type_casting_traits {
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| /external/clang/lib/Sema/ |
| D | SemaChecking.cpp | 7340 const llvm::fltSemantics &Tgt) { in IsSameFloatAfterCast() argument
7345 truncated.convert(Tgt, llvm::APFloat::rmNearestTiesToEven, &ignored); in IsSameFloatAfterCast()
7357 const llvm::fltSemantics &Tgt) { in IsSameFloatAfterCast() argument
7359 return IsSameFloatAfterCast(value.getFloat(), Src, Tgt); in IsSameFloatAfterCast()
7363 if (!IsSameFloatAfterCast(value.getVectorElt(i), Src, Tgt)) in IsSameFloatAfterCast()
7369 return (IsSameFloatAfterCast(value.getComplexFloatReal(), Src, Tgt) && in IsSameFloatAfterCast()
7370 IsSameFloatAfterCast(value.getComplexFloatImag(), Src, Tgt)); in IsSameFloatAfterCast()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenDAGPatterns.cpp | 1124 CodeGenTarget &Tgt = TP.getDAGPatterns().getTargetInfo(); in UpdateNodeTypeFromInst() local
1125 return UpdateNodeType(ResNo, Tgt.getRegisterClass(RC).getValueTypes(), TP); in UpdateNodeTypeFromInst()
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| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | CodeGenDAGPatterns.cpp | 1557 CodeGenTarget &Tgt = TP.getDAGPatterns().getTargetInfo(); in UpdateNodeTypeFromInst() local
1558 return UpdateNodeType(ResNo, Tgt.getRegisterClass(RC).getValueTypes(), TP); in UpdateNodeTypeFromInst()
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