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Searched refs:TrueReg (Results 1 – 25 of 25) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp745 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
758 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
783 ArrayRef<MachineOperand> Cond, unsigned TrueReg, in insertSelect() argument
791 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in insertSelect()
843 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect()
844 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect()
2205 unsigned TrueReg, unsigned FalseReg, in selectReg() argument
2212 return Imm1 < Imm2 ? TrueReg : FalseReg; in selectReg()
2214 return Imm1 > Imm2 ? TrueReg : FalseReg; in selectReg()
2216 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
[all …]
DPPCMIPeephole.cpp402 unsigned TrueReg = in simplifyCode() local
404 if (!TargetRegisterInfo::isVirtualRegister(TrueReg)) in simplifyCode()
406 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode()
465 unsigned TrueReg = in simplifyCode() local
467 if (!TargetRegisterInfo::isVirtualRegister(TrueReg)) in simplifyCode()
469 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode()
DPPCInstrInfo.h240 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstructionSelector.cpp639 auto TrueReg = MIB->getOperand(2).getReg(); in selectSelect() local
641 assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) && in selectSelect()
642 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) && in selectSelect()
646 .addUse(TrueReg) in selectSelect()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp244 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
250 TrueReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg)); in LowerFPToInt()
295 BuildMI(TrueMBB, DL, TII.get(IConst), TrueReg) in LowerFPToInt()
300 .addReg(TrueReg) in LowerFPToInt()
DWebAssemblyFastISel.cpp861 unsigned TrueReg = getRegForValue(Select->getTrueValue()); in selectSelect() local
862 if (TrueReg == 0) in selectSelect()
870 std::swap(TrueReg, FalseReg); in selectSelect()
904 .addReg(TrueReg) in selectSelect()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.h264 unsigned TrueReg, unsigned FalseReg,
271 unsigned TrueReg, unsigned FalseReg) const override;
276 unsigned TrueReg, unsigned FalseReg) const;
DSIInstrInfo.cpp683 unsigned TrueReg, in insertVectorSelect() argument
695 .addReg(TrueReg) in insertVectorSelect()
707 .addReg(TrueReg) in insertVectorSelect()
718 .addReg(TrueReg) in insertVectorSelect()
730 .addReg(TrueReg) in insertVectorSelect()
741 .addReg(TrueReg) in insertVectorSelect()
756 .addReg(TrueReg) in insertVectorSelect()
770 .addReg(TrueReg) in insertVectorSelect()
1786 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
1793 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg); in canInsertSelect()
[all …]
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyFastISel.cpp724 unsigned TrueReg = getRegForValue(Select->getTrueValue()); in selectSelect() local
725 if (TrueReg == 0) in selectSelect()
733 std::swap(TrueReg, FalseReg); in selectSelect()
763 .addReg(TrueReg) in selectSelect()
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.h181 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
DPPCInstrInfo.cpp687 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
703 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
728 ArrayRef<MachineOperand> Cond, unsigned TrueReg, in insertSelect() argument
739 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in insertSelect()
791 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect()
792 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.cpp636 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
648 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
671 unsigned TrueReg, in insertSelect() argument
689 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg); in insertSelect()
691 TrueReg = TReg; in insertSelect()
700 .addReg(FalseReg).addReg(TrueReg) in insertSelect()
DSystemZInstrInfo.h218 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
DSystemZISelLowering.cpp6101 unsigned TrueReg = MIIt->getOperand(1).getReg(); in createPHIsForSelects() local
6108 std::swap(TrueReg, FalseReg); in createPHIsForSelects()
6110 if (RegRewriteTable.find(TrueReg) != RegRewriteTable.end()) in createPHIsForSelects()
6111 TrueReg = RegRewriteTable[TrueReg].first; in createPHIsForSelects()
6117 .addReg(TrueReg).addMBB(TrueMBB) in createPHIsForSelects()
6121 RegRewriteTable[DestReg] = std::make_pair(TrueReg, FalseReg); in createPHIsForSelects()
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.h158 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
DAArch64InstrInfo.cpp368 unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, in canInsertSelect() argument
373 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
387 if (canFoldIntoCSel(MRI, TrueReg)) in canInsertSelect()
411 unsigned TrueReg, unsigned FalseReg) const { in insertSelect() argument
514 unsigned FoldedOpc = canFoldIntoCSel(MRI, TrueReg, &NewVReg); in insertSelect()
519 TrueReg = FalseReg; in insertSelect()
533 MRI.constrainRegClass(TrueReg, RC); in insertSelect()
537 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(TrueReg).addReg(FalseReg).addImm( in insertSelect()
/external/llvm/include/llvm/Target/
DTargetInstrInfo.h690 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
714 unsigned TrueReg, unsigned FalseReg) const { in insertSelect() argument
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DTargetInstrInfo.h758 ArrayRef<MachineOperand> Cond, unsigned TrueReg, in canInsertSelect() argument
782 unsigned TrueReg, unsigned FalseReg) const { in insertSelect() argument
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64InstrInfo.h188 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
DAArch64InstrInfo.cpp488 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
494 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
508 if (canFoldIntoCSel(MRI, TrueReg)) in canInsertSelect()
532 unsigned TrueReg, unsigned FalseReg) const { in insertSelect() argument
635 unsigned FoldedOpc = canFoldIntoCSel(MRI, TrueReg, &NewVReg); in insertSelect()
640 TrueReg = FalseReg; in insertSelect()
654 MRI.constrainRegClass(TrueReg, RC); in insertSelect()
659 .addReg(TrueReg) in insertSelect()
/external/llvm/lib/Target/X86/
DX86InstrInfo.h327 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
DX86InstrInfo.cpp4279 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
4293 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
4316 ArrayRef<MachineOperand> Cond, unsigned TrueReg, in insertSelect() argument
4323 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg); in insertSelect()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrInfo.h346 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
DX86InstrInfo.cpp2899 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
2913 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
2936 ArrayRef<MachineOperand> Cond, unsigned TrueReg, in insertSelect() argument
2945 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg); in insertSelect()
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp5204 unsigned TrueReg = MI.getOperand(1).getReg(); in emitSelect() local
5233 .addReg(TrueReg).addMBB(StartMBB) in emitSelect()