| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86RegisterBankInfo.cpp | 206 const LLT Ty0 = MRI.getType(Op0.getReg()); in getInstrMapping() local
208 OpRegBankIdx[0] = getPartialMappingIdx(Ty0, /* isFP */ true); in getInstrMapping()
216 const LLT Ty0 = MRI.getType(Op0.getReg()); in getInstrMapping() local
219 bool isFPTrunc = (Ty0.getSizeInBits() == 32 || Ty0.getSizeInBits() == 64) && in getInstrMapping()
222 Ty0.getSizeInBits() == 128 && in getInstrMapping()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64LegalizerInfo.cpp | 105 const LLT &Ty0 = Query.Types[0]; in AArch64LegalizerInfo() local
107 if (Ty0 != s32 && Ty0 != s64 && Ty0 != p0) in AArch64LegalizerInfo()
123 const LLT &Ty0 = Query.Types[0]; in AArch64LegalizerInfo() local
129 return isPowerOf2_32(Ty0.getSizeInBits()) && in AArch64LegalizerInfo()
130 (Ty0.getSizeInBits() == 1 || Ty0.getSizeInBits() >= 8); in AArch64LegalizerInfo()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 125 const LLT &Ty0 = Query.Types[0]; in AMDGPULegalizerInfo() local
129 switch (Ty0.getSizeInBits()) { in AMDGPULegalizerInfo()
177 const LLT &Ty0 = Query.Types[0]; in AMDGPULegalizerInfo() local
179 return (Ty0.getSizeInBits() % 32 == 0) && in AMDGPULegalizerInfo()
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| D | AMDGPURewriteOutArguments.cpp | 109 bool isVec3ToVec4Shuffle(Type *Ty0, Type* Ty1) const;
210 bool AMDGPURewriteOutArguments::isVec3ToVec4Shuffle(Type *Ty0, Type* Ty1) const { in isVec3ToVec4Shuffle() argument
211 VectorType *VT0 = dyn_cast<VectorType>(Ty0); in isVec3ToVec4Shuffle()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Vectorize/ |
| D | LoopVectorizationLegality.cpp | 425 static Type *getWiderType(const DataLayout &DL, Type *Ty0, Type *Ty1) { in getWiderType() argument
426 Ty0 = convertPointerToIntegerType(DL, Ty0); in getWiderType()
428 if (Ty0->getScalarSizeInBits() > Ty1->getScalarSizeInBits()) in getWiderType()
429 return Ty0; in getWiderType()
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| D | SLPVectorizer.cpp | 375 Type *Ty0 = cast<Instruction>(VL[BaseIndex])->getOperand(0)->getType(); in getSameOpcode() local
377 if (Ty0 == Ty1) { in getSameOpcode()
1794 Type *Ty0 = VL0->getOperand(0)->getType(); in buildTree_rec() local
1797 if (Ty0 != CurTy) { in buildTree_rec()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZTargetTransformInfo.cpp | 505 static unsigned getElSizeLog2Diff(Type *Ty0, Type *Ty1) { in getElSizeLog2Diff() argument
506 unsigned Bits0 = Ty0->getScalarSizeInBits(); in getElSizeLog2Diff()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonLoopIdiomRecognition.cpp | 1093 Type *Ty0 = P->getIncomingValue(0)->getType(); in promoteTypes() local
1095 if (PTy != Ty0) { in promoteTypes()
1096 assert(Ty0 == DestTy); in promoteTypes()
1098 P->mutateType(Ty0); in promoteTypes()
1104 P->mutateType(Ty0); in promoteTypes()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineSimplifyDemanded.cpp | 1538 auto *Ty0 = II->getArgOperand(0)->getType(); in SimplifyDemandedVectorElts() local
1539 unsigned InnerVWidth = Ty0->getVectorNumElements(); in SimplifyDemandedVectorElts()
1542 unsigned NumLanes = Ty0->getPrimitiveSizeInBits() / 128; in SimplifyDemandedVectorElts()
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| /external/llvm/lib/Transforms/Vectorize/ |
| D | LoopVectorize.cpp | 4508 static Type *getWiderType(const DataLayout &DL, Type *Ty0, Type *Ty1) { in getWiderType() argument
4509 Ty0 = convertPointerToIntegerType(DL, Ty0); in getWiderType()
4511 if (Ty0->getScalarSizeInBits() > Ty1->getScalarSizeInBits()) in getWiderType()
4512 return Ty0; in getWiderType()
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| D | SLPVectorizer.cpp | 1301 Type *Ty0 = cast<Instruction>(VL0)->getOperand(0)->getType(); in buildTree_rec() local
1304 if (Ty0 != CurTy) { in buildTree_rec()
|