1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Meson GXL and GXM USB2 PHY driver
4 *
5 * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
6 * Copyright (C) 2018 BayLibre, SAS
7 * Author: Neil Armstrong <narmstron@baylibre.com>
8 */
9
10 #include <common.h>
11 #include <asm/io.h>
12 #include <bitfield.h>
13 #include <dm.h>
14 #include <errno.h>
15 #include <generic-phy.h>
16 #include <regmap.h>
17 #include <power/regulator.h>
18 #include <clk.h>
19
20 #include <linux/bitops.h>
21 #include <linux/compat.h>
22
23 /* bits [31:27] are read-only */
24 #define U2P_R0 0x0
25 #define U2P_R0_BYPASS_SEL BIT(0)
26 #define U2P_R0_BYPASS_DM_EN BIT(1)
27 #define U2P_R0_BYPASS_DP_EN BIT(2)
28 #define U2P_R0_TXBITSTUFF_ENH BIT(3)
29 #define U2P_R0_TXBITSTUFF_EN BIT(4)
30 #define U2P_R0_DM_PULLDOWN BIT(5)
31 #define U2P_R0_DP_PULLDOWN BIT(6)
32 #define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7)
33 #define U2P_R0_DP_VBUS_VLD_EXT BIT(8)
34 #define U2P_R0_ADP_PRB_EN BIT(9)
35 #define U2P_R0_ADP_DISCHARGE BIT(10)
36 #define U2P_R0_ADP_CHARGE BIT(11)
37 #define U2P_R0_DRV_VBUS BIT(12)
38 #define U2P_R0_ID_PULLUP BIT(13)
39 #define U2P_R0_LOOPBACK_EN_B BIT(14)
40 #define U2P_R0_OTG_DISABLE BIT(15)
41 #define U2P_R0_COMMON_ONN BIT(16)
42 #define U2P_R0_FSEL_MASK GENMASK(19, 17)
43 #define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20)
44 #define U2P_R0_POWER_ON_RESET BIT(22)
45 #define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23)
46 #define U2P_R0_ID_SET_ID_DQ BIT(25)
47 #define U2P_R0_ATE_RESET BIT(26)
48 #define U2P_R0_FSV_MINUS BIT(27)
49 #define U2P_R0_FSV_PLUS BIT(28)
50 #define U2P_R0_BYPASS_DM_DATA BIT(29)
51 #define U2P_R0_BYPASS_DP_DATA BIT(30)
52
53 #define U2P_R1 0x4
54 #define U2P_R1_BURN_IN_TEST BIT(0)
55 #define U2P_R1_ACA_ENABLE BIT(1)
56 #define U2P_R1_DCD_ENABLE BIT(2)
57 #define U2P_R1_VDAT_SRC_EN_B BIT(3)
58 #define U2P_R1_VDAT_DET_EN_B BIT(4)
59 #define U2P_R1_CHARGES_SEL BIT(5)
60 #define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6)
61 #define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7)
62 #define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9)
63 #define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11)
64 #define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13)
65 #define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17)
66 #define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21)
67 #define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23)
68 #define U2P_R1_SQRX_TUNE_MASK GENMASK(28, 26)
69 #define U2P_R1_COMP_DIS_TUNE_MASK GENMASK(31, 29)
70
71 /* bits [31:14] are read-only */
72 #define U2P_R2 0x8
73 #define U2P_R2_TESTDATA_IN_MASK GENMASK(7, 0)
74 #define U2P_R2_TESTADDR_MASK GENMASK(11, 8)
75 #define U2P_R2_TESTDATA_OUT_SEL BIT(12)
76 #define U2P_R2_TESTCLK BIT(13)
77 #define U2P_R2_TESTDATA_OUT_MASK GENMASK(17, 14)
78 #define U2P_R2_ACA_PIN_RANGE_C BIT(18)
79 #define U2P_R2_ACA_PIN_RANGE_B BIT(19)
80 #define U2P_R2_ACA_PIN_RANGE_A BIT(20)
81 #define U2P_R2_ACA_PIN_GND BIT(21)
82 #define U2P_R2_ACA_PIN_FLOAT BIT(22)
83 #define U2P_R2_CHARGE_DETECT BIT(23)
84 #define U2P_R2_DEVICE_SESSION_VALID BIT(24)
85 #define U2P_R2_ADP_PROBE BIT(25)
86 #define U2P_R2_ADP_SENSE BIT(26)
87 #define U2P_R2_SESSION_END BIT(27)
88 #define U2P_R2_VBUS_VALID BIT(28)
89 #define U2P_R2_B_VALID BIT(29)
90 #define U2P_R2_A_VALID BIT(30)
91 #define U2P_R2_ID_DIG BIT(31)
92
93 #define U2P_R3 0xc
94
95 #define RESET_COMPLETE_TIME 500
96
97 struct phy_meson_gxl_usb2_priv {
98 struct regmap *regmap;
99 #if CONFIG_IS_ENABLED(DM_REGULATOR)
100 struct udevice *phy_supply;
101 #endif
102 #if CONFIG_IS_ENABLED(CLK)
103 struct clk clk;
104 #endif
105 };
106
phy_meson_gxl_usb2_reset(struct phy_meson_gxl_usb2_priv * priv)107 static void phy_meson_gxl_usb2_reset(struct phy_meson_gxl_usb2_priv *priv)
108 {
109 uint val;
110
111 regmap_read(priv->regmap, U2P_R0, &val);
112
113 /* reset the PHY and wait until settings are stabilized */
114 val |= U2P_R0_POWER_ON_RESET;
115 regmap_write(priv->regmap, U2P_R0, val);
116 udelay(RESET_COMPLETE_TIME);
117
118 val &= ~U2P_R0_POWER_ON_RESET;
119 regmap_write(priv->regmap, U2P_R0, val);
120 udelay(RESET_COMPLETE_TIME);
121 }
122
123 static void
phy_meson_gxl_usb2_set_host_mode(struct phy_meson_gxl_usb2_priv * priv)124 phy_meson_gxl_usb2_set_host_mode(struct phy_meson_gxl_usb2_priv *priv)
125 {
126 uint val;
127
128 regmap_read(priv->regmap, U2P_R0, &val);
129 val |= U2P_R0_DM_PULLDOWN;
130 val |= U2P_R0_DP_PULLDOWN;
131 val &= ~U2P_R0_ID_PULLUP;
132 regmap_write(priv->regmap, U2P_R0, val);
133
134 phy_meson_gxl_usb2_reset(priv);
135 }
136
phy_meson_gxl_usb2_power_on(struct phy * phy)137 static int phy_meson_gxl_usb2_power_on(struct phy *phy)
138 {
139 struct udevice *dev = phy->dev;
140 struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
141 uint val;
142
143 regmap_read(priv->regmap, U2P_R0, &val);
144 /* power on the PHY by taking it out of reset mode */
145 val &= ~U2P_R0_POWER_ON_RESET;
146 regmap_write(priv->regmap, U2P_R0, val);
147
148 phy_meson_gxl_usb2_set_host_mode(priv);
149
150 #if CONFIG_IS_ENABLED(DM_REGULATOR)
151 if (priv->phy_supply) {
152 int ret = regulator_set_enable(priv->phy_supply, true);
153 if (ret)
154 return ret;
155 }
156 #endif
157
158 return 0;
159 }
160
phy_meson_gxl_usb2_power_off(struct phy * phy)161 static int phy_meson_gxl_usb2_power_off(struct phy *phy)
162 {
163 struct udevice *dev = phy->dev;
164 struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
165 uint val;
166
167 regmap_read(priv->regmap, U2P_R0, &val);
168 /* power off the PHY by putting it into reset mode */
169 val |= U2P_R0_POWER_ON_RESET;
170 regmap_write(priv->regmap, U2P_R0, val);
171
172 #if CONFIG_IS_ENABLED(DM_REGULATOR)
173 if (priv->phy_supply) {
174 int ret = regulator_set_enable(priv->phy_supply, false);
175 if (ret) {
176 pr_err("Error disabling PHY supply\n");
177 return ret;
178 }
179 }
180 #endif
181
182 return 0;
183 }
184
185 struct phy_ops meson_gxl_usb2_phy_ops = {
186 .power_on = phy_meson_gxl_usb2_power_on,
187 .power_off = phy_meson_gxl_usb2_power_off,
188 };
189
meson_gxl_usb2_phy_probe(struct udevice * dev)190 int meson_gxl_usb2_phy_probe(struct udevice *dev)
191 {
192 struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
193 int ret;
194
195 ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
196 if (ret)
197 return ret;
198
199 #if CONFIG_IS_ENABLED(CLK)
200 ret = clk_get_by_index(dev, 0, &priv->clk);
201 if (ret < 0)
202 return ret;
203
204 ret = clk_enable(&priv->clk);
205 if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
206 pr_err("failed to enable PHY clock\n");
207 clk_free(&priv->clk);
208 return ret;
209 }
210 #endif
211
212 #if CONFIG_IS_ENABLED(DM_REGULATOR)
213 ret = device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
214 if (ret && ret != -ENOENT) {
215 pr_err("Failed to get PHY regulator\n");
216 return ret;
217 }
218 #endif
219
220 return 0;
221 }
222
223 static const struct udevice_id meson_gxl_usb2_phy_ids[] = {
224 { .compatible = "amlogic,meson-gxl-usb2-phy" },
225 { }
226 };
227
228 U_BOOT_DRIVER(meson_gxl_usb2_phy) = {
229 .name = "meson_gxl_usb2_phy",
230 .id = UCLASS_PHY,
231 .of_match = meson_gxl_usb2_phy_ids,
232 .probe = meson_gxl_usb2_phy_probe,
233 .ops = &meson_gxl_usb2_phy_ops,
234 .priv_auto_alloc_size = sizeof(struct phy_meson_gxl_usb2_priv),
235 };
236