| /external/u-boot/drivers/serial/ |
| D | Kconfig | 12 meaning of either setting the baudrate for the early debug UART
32 In various cases, we need to specify which of the UART devices that
41 In very space-constrained devices even the full UART driver is too
42 large. In this case the debug UART can still be used in some cases.
43 This option enables the full UART in U-Boot, so if is it disabled,
44 the full UART driver will be omitted, thus saving space.
51 In very space-constrained devices even the full UART driver is too
52 large. In this case the debug UART can still be used in some cases.
53 This option enables the full UART in SPL, so if is it disabled,
54 the full UART driver will be omitted, thus saving space.
[all …]
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| D | serial_pxa.c | 177 #define pxa_uart(uart, UART) \ argument
180 return pxa_init_dev(UART##_INDEX); \
185 return pxa_setbrg_dev(UART##_INDEX); \
190 return pxa_putc_dev(UART##_INDEX, c); \
195 return pxa_puts_dev(UART##_INDEX, s); \
200 return pxa_getc_dev(UART##_INDEX); \
205 return pxa_tstc_dev(UART##_INDEX); \
221 #define pxa_uart_multi(uart, UART) \ argument
222 pxa_uart(uart, UART) \
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| /external/u-boot/board/congatec/conga-qeval20-qa3-e3845/ |
| D | README | 2 U-Boot console UART selection:
6 configurations (defconfig files). The only difference is the UART that
7 is used as the U-Boot console UART. The default defconfig file:
13 board (conga-QEVAL). This UART is the one provided with a SubD9
18 provides the U-Boot console on the BayTrail internal legacy UART,
21 RS232 level shifters. So a TTL-USB UART adapter does not work in
23 RS232 level signals of the PC UART via some adapter cable.
|
| /external/u-boot/arch/arm/ |
| D | Kconfig.debug | 16 bool "Low-level debugging via 8250 UART"
19 their output to an 8250 UART. You can use this option
20 to provide the parameters for the 8250 UART rather than
41 hex "Physical base address of debug UART"
51 int "Register offset shift for the 8250 debug UART"
56 bool "Use 32-bit accesses for 8250 UART"
61 bool "Enable flow control for 8250 UART"
|
| /external/u-boot/board/solidrun/clearfog/ |
| D | README | 29 - UART: 01001 [1]
31 [1]: According to SolidRun's manual, 11110 should be used for UART booting on
36 Boot from UART:
42 Set the SW1 DIP switches to UART boot (see above).
48 Use the correct UART device node for /dev/ttyUSBX.
|
| /external/u-boot/board/kobol/helios4/ |
| D | README | 29 - UART: 11110
31 Boot from UART:
37 Set the SW1 DIP switches to UART boot (see above).
43 Use the correct UART device node for /dev/ttyUSBX.
|
| /external/u-boot/doc/device-tree-bindings/serial/ |
| D | 8250.txt | 1 * UART (Universal Asynchronous Receiver/Transmitter)
26 - clock-frequency : the input clock frequency for the UART
32 - current-speed : the current active speed of the UART.
37 accesses to the UART (e.g. TI davinci).
42 - fifo-size: the fifo size of the UART.
|
| D | altera_uart.txt | 1 Altera UART
7 - clock-frequency : frequency of the clock input to the UART
|
| D | xilinx_uartlite.txt | 5 - reg: Should contain UART controller registers location and length.
6 - interrupts: Should contain UART controller interrupts.
|
| D | bcm2835-aux-uart.txt | 1 * BCM283x mini UART
6 - clock: input clock frequency for the UART (used to calculate the baud
|
| D | pl01x.txt | 1 * ARM AMBA Primecell PL011 & PL010 serial UART
6 - clock: input clock frequency for the UART (used to calculate the baud
|
| D | qca,ar9330-uart.txt | 1 * Qualcomm Atheros AR9330 High-Speed UART
12 Each UART port must have an alias correctly numbered in "aliases"
|
| D | omap_serial.txt | 1 OMAP UART controller
18 - clock-frequency : frequency of the clock input to the UART
|
| /external/u-boot/arch/mips/mach-bmips/ |
| D | Kconfig | 134 ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and
145 ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and
156 ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and a
167 ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs,
178 ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs,
189 ethernet ports, 3 USB ports, 1 UART, GPIO buttons and LEDs, and
200 ethernet ports, 1 UART, GPIO buttons and LEDs, and a BCM43225
211 ethernet ports, 2 USB ports, 1 UART, GPIO buttons and LEDs, and a
222 ethernet ports, 1 UART, GPIO buttons and LEDs, and a BCM4312
233 ethernet ports, 2 USB ports, 1 UART, GPIO buttons and LEDs, and
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| /external/u-boot/arch/arm/dts/ |
| D | meson-gxl-s905x-khadas-vim.dts | 116 gpio-line-names = "UART TX",
117 "UART RX",
163 "Bluetooth UART TX", "Bluetooth UART RX",
164 "Bluetooth UART CTS", "Bluetooth UART RTS",
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| D | kirkwood-openrd.dtsi | 61 * mode for the second UART.
66 * To use the second UART, you need to change also
78 * SelUARTorSD selects between the second UART
81 * Low: UART
|
| /external/tensorflow/tensorflow/lite/experimental/micro/testing/ |
| D | bluepill.robot | 8 ${UART} sysbus.cpu.uartSemihosting variable
12 …cumentation] Runs a Bluepill test and waits for a specific string on the semihosting UART
20 Create Terminal Tester ${UART} timeout=30
|
| /external/u-boot/arch/x86/cpu/baytrail/ |
| D | Kconfig | 31 bool "Enable the SoC integrated legacy UART"
33 There is a legacy UART integrated into the Bay Trail SoC.
35 reason, it is recommended that the UART port be used for
|
| /external/u-boot/arch/arm/mach-bcm283x/ |
| D | Kconfig | 54 mini UART (rather than PL011) for the serial console. This is the
55 default on the RPi Zero W. To enable the UART console, the following
71 VideoCore firmware to select the PL011 UART for the console by:
93 mini UART (rather than PL011) for the serial console. This is the
94 default on the RPi 3. To enable the UART console, the following non-
109 mini UART (rather than PL011) for the serial console. This is the
110 default on the RPi 3. To enable the UART console, the following non-
|
| /external/u-boot/arch/arm/mach-rockchip/rk3288/ |
| D | Kconfig | 40 provide access to display pins, I2C, SPI, UART and GPIOs.
49 provide access to display pins, I2C, SPI, UART and GPIOs.
58 provide access to display pins, I2C, SPI, UART and GPIOs.
67 I2C, SPI, UART, GPIOs and fan control.
84 2GB DDR3. Expansion connectors provide access to I2C, SPI, UART,
110 provide access to display pins, I2C, SPI, UART and GPIOs.
128 I2C, SPI, UART, GPIOs.
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| /external/u-boot/arch/arm/mach-tegra/tegra210/ |
| D | pinmux.c | 89 PIN(UART2_TX_PG0, UARTB, I2S4A, SPDIF, UART),
90 PIN(UART2_RX_PG1, UARTB, I2S4A, SPDIF, UART),
91 PIN(UART2_RTS_PG2, UARTB, I2S4A, RSVD2, UART),
92 PIN(UART2_CTS_PG3, UARTB, I2S4A, RSVD2, UART),
97 PIN(UART4_TX_PI4, UARTD, UART, RSVD2, RSVD3),
98 PIN(UART4_RX_PI5, UARTD, UART, RSVD2, RSVD3),
99 PIN(UART4_RTS_PI6, UARTD, UART, RSVD2, RSVD3),
100 PIN(UART4_CTS_PI7, UARTD, UART, RSVD2, RSVD3),
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| /external/u-boot/board/ti/ks2_evm/ |
| D | README | 31 | |DDR3 |NAND |MSM SRAM |ETH ports |UART |I2C |SPI |
65 - UART boot
70 Texas Instruments code composure studio (CCS) and for UART boot.
173 Load and Run U-Boot on keystone EVMs using UART download
176 Open BMC and regular UART terminals.
178 1. On the regular UART port start xmodem transfer of the u-boot.bin
179 2. Using BMC terminal set the ARM-UART bootmode and reboot the EVM
182 3. When xmodem is complete you should see the U-Boot starts on the UART port
187 Open BMC and regular UART terminals.
|
| /external/u-boot/board/freescale/ls1012ardb/ |
| D | README | 35 - UART
36 - The LS1012A processor consists of two UART controllers,
71 - UART
72 - The LS1012A processor consists of two UART controllers,
|
| /external/u-boot/board/Barix/ipam390/ |
| D | ipam390-ais-uart.cfg | 8 ; SPIMASTER,I2CMASTER,EMIFA,NAND,EMAC,UART,PCI,HPI,USB,MMC_SD,VLYNQ,RAW
9 BootMode=UART
43 ; of the current booting peripheral (I2C, SPI, or UART).
52 ; UART: |------24|------16|-------8|-------0|
118 ; the I2C, SPI, or UART modes are being used. This ensures that
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| /external/u-boot/board/freescale/ls1012afrdm/ |
| D | README | 30 - UART
31 - UART (Console): UART1 (Without flow control) for console
40 - 24 MHz for SC16IS740IPW SPI to Dual UART bridge
|