Searched refs:UCVTF (Results 1 – 10 of 10) sorted by relevance
| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 1511 UCVTF = FPIntegerConvertFixed | 0x00030000, enumerator
1512 UCVTF_hw = UCVTF | FP16,
1513 UCVTF_hx = UCVTF | SixtyFourBits | FP16,
1514 UCVTF_sw = UCVTF,
1515 UCVTF_sx = UCVTF | SixtyFourBits,
1516 UCVTF_dw = UCVTF | FP64,
1517 UCVTF_dx = UCVTF | SixtyFourBits | FP64,
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| D | disasm-aarch64.cc | 2500 FORMAT(UCVTF, "ucvtf") in VisitNEON2RegMiscFP16()
3978 FORMAT(UCVTF, "ucvtf") in VisitNEONScalar2RegMiscFP16()
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| D | assembler-aarch64.cc | 3104 Emit(SF(rn) | FPType(vd) | UCVTF | Rn(rn) | Rd(vd)); in ucvtf()
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 1286 UCVTF = FPIntegerConvertFixed | 0x00030000, enumerator
1287 UCVTF_sw = UCVTF,
1288 UCVTF_sx = UCVTF | SixtyFourBits,
1289 UCVTF_dw = UCVTF | FP64,
1290 UCVTF_dx = UCVTF | SixtyFourBits | FP64,
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| D | assembler-arm64.cc | 3231 Emit(SF(rn) | FPType(fd) | UCVTF | Rn(rn) | Rd(fd)); in ucvtf()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 573 // SCVTF,UCVTF V,V
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| D | AArch64InstrInfo.td | 2556 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
2895 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
3373 defm UCVTF : SIMDFPTwoScalarCVT< 1, 0, 0b11101, "ucvtf", AArch64uitof>;
3447 SDPatternOperator loadop, Instruction UCVTF,
3453 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3460 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3489 // UCVTF on floating point registers (both source and destination
4681 defm UCVTF : SIMDFPScalarRShift<1, 0b11100, "ucvtf">;
4789 defm UCVTF : SIMDVectorRShiftToFP<1, 0b11100, "ucvtf",
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 575 // SCVTF,UCVTF V,V
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| D | AArch64InstrInfo.td | 2837 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
3159 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
3650 defm UCVTF : SIMDFPTwoScalarCVT< 1, 0, 0b11101, "ucvtf", AArch64uitof>;
3752 SDPatternOperator loadop, Instruction UCVTF,
3758 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3765 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3794 // UCVTF on floating point registers (both source and destination
5016 defm UCVTF : SIMDFPScalarRShift<1, 0b11100, "ucvtf">;
5159 defm UCVTF : SIMDVectorRShiftToFP<1, 0b11100, "ucvtf",
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 3807 ### UCVTF ### subsection
3814 ### UCVTF ### subsection
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