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Searched refs:UMIN (Results 1 – 25 of 70) sorted by relevance

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/external/libhevc/common/arm64/
Dihevc_sao_edge_offset_class1.s183UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
194UMIN v1.8h, v1.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
205UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
208UMIN v28.8h, v28.8h , v4.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_…
237UMIN v26.8h, v26.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
243UMIN v28.8h, v28.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
313UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
319UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
348UMIN v26.8h, v26.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
Dihevc_sao_edge_offset_class1_chroma.s219UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
240UMIN v28.8h, v28.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
253UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
256UMIN v28.8h, v28.8h , v4.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_…
297UMIN v26.8h, v26.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
303UMIN v28.8h, v28.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
394UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
406UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
447UMIN v26.8h, v26.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
Dihevc_sao_edge_offset_class2.s342UMIN v20.8h, v20.8h , v4.8h //I pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u…
351UMIN v22.8h, v22.8h , v4.8h //I pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u…
439UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
444UMIN v20.8h, v20.8h , v4.8h //III pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq…
450UMIN v28.8h, v28.8h , v4.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_…
463UMIN v18.8h, v18.8h , v4.8h //III pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq…
520UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
526UMIN v5.8h, v5.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
656UMIN v28.8h, v28.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
662UMIN v30.8h, v30.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
[all …]
Dihevc_sao_edge_offset_class0.s221UMIN v18.8h, v18.8h , v6.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
232UMIN v21.8h, v21.8h , v6.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
241UMIN v0.8h, v0.8h , v6.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
248UMIN v28.8h, v28.8h , v6.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_…
322UMIN v28.8h, v28.8h , v6.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
Dihevc_sao_edge_offset_class3.s354UMIN v20.8h, v20.8h , v4.8h //I pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u…
360UMIN v22.8h, v22.8h , v4.8h //I pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u…
458UMIN v28.8h, v28.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
468UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_…
475UMIN v20.8h, v20.8h , v4.8h //III pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq…
484UMIN v22.8h, v22.8h , v4.8h //III pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq…
550UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
554UMIN v22.8h, v22.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
694UMIN v28.8h, v28.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
700UMIN v30.8h, v30.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
[all …]
Dihevc_sao_edge_offset_class0_chroma.s259UMIN v18.8h, v18.8h , v6.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
269UMIN v19.8h, v19.8h , v6.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
292UMIN v28.8h, v28.8h , v6.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
304UMIN v30.8h, v30.8h , v6.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_…
436UMIN v18.8h, v18.8h , v6.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
465UMIN v24.8h, v24.8h , v6.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
Dihevc_sao_edge_offset_class3_chroma.s471UMIN v20.8h, v20.8h , v4.8h //I pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u…
479UMIN v18.8h, v18.8h , v4.8h //I pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u…
621UMIN v28.8h, v28.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
636UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_…
643UMIN v20.8h, v20.8h , v4.8h //III pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq…
650UMIN v18.8h, v18.8h , v4.8h //III pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq…
732UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
736UMIN v18.8h, v18.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
921UMIN v28.8h, v28.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
927UMIN v30.8h, v30.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
[all …]
Dihevc_sao_edge_offset_class2_chroma.s488UMIN v20.8h, v20.8h , v4.8h //I pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u…
493UMIN v18.8h, v18.8h , v4.8h //I pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u…
621UMIN v28.8h, v28.8h , v4.8h //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_…
643UMIN v26.8h, v26.8h , v4.8h //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_…
656UMIN v20.8h, v20.8h , v4.8h //III pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq…
664UMIN v18.8h, v18.8h , v4.8h //III pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq…
742UMIN v20.8h, v20.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
746UMIN v18.8h, v18.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
909UMIN v28.8h, v28.8h , v4.8h //pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16…
914UMIN v26.8h, v26.8h , v4.8h //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16…
[all …]
/external/u-boot/arch/x86/include/asm/arch-baytrail/acpi/
Dsouthcluster.asl149 CreateQwordField(MCRS, ^UMEM._MIN, UMIN)
154 Store(0xc00000000, UMIN)
156 Add(UMIN, Subtract(ULEN, 1), UMAX)
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp2107 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; in getMinMaxReductionCost()
2121 {ISD::UMIN, MVT::v2i64, 8}, // The data reported by the IACA is "8.6" in getMinMaxReductionCost()
2123 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8" in getMinMaxReductionCost()
2125 {ISD::UMIN, MVT::v8i16, 2}, in getMinMaxReductionCost()
2133 {ISD::UMIN, MVT::v2i64, 3}, in getMinMaxReductionCost()
2135 {ISD::UMIN, MVT::v4i32, 1}, in getMinMaxReductionCost()
2137 {ISD::UMIN, MVT::v8i16, 1}, in getMinMaxReductionCost()
2139 {ISD::UMIN, MVT::v8i32, 3}, in getMinMaxReductionCost()
2144 {ISD::UMIN, MVT::v4i64, 2}, in getMinMaxReductionCost()
2146 {ISD::UMIN, MVT::v8i32, 1}, in getMinMaxReductionCost()
[all …]
/external/strace/xlat/
Datomic_ops.in9 { OR1K_ATOMIC_UMIN, "UMIN" },
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dvec_minmax_match.ll192 ; (X <u C1) ? C1 : UMIN(X, C2) ==> UMAX(UMIN(X, C2), C1)
207 ; (X >u C1) ? C1 : UMAX(X, C2) ==> UMIN(UMAX(X, C2), C1)
/external/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_opcode_tmp.h141 OP12(UMIN)
Dtgsi_info_opcodes.h134 OPCODE(1, 2, COMP, UMIN)
/external/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h984 X86_INTRINSIC_DATA(avx512_mask_pminu_b_128, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
985 X86_INTRINSIC_DATA(avx512_mask_pminu_b_256, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
986 X86_INTRINSIC_DATA(avx512_mask_pminu_b_512, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
987 X86_INTRINSIC_DATA(avx512_mask_pminu_d_128, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
988 X86_INTRINSIC_DATA(avx512_mask_pminu_d_256, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
989 X86_INTRINSIC_DATA(avx512_mask_pminu_d_512, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
990 X86_INTRINSIC_DATA(avx512_mask_pminu_q_128, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
991 X86_INTRINSIC_DATA(avx512_mask_pminu_q_256, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
992 X86_INTRINSIC_DATA(avx512_mask_pminu_q_512, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
993 X86_INTRINSIC_DATA(avx512_mask_pminu_w_128, INTR_TYPE_2OP_MASK, ISD::UMIN, 0),
[all …]
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h325 SMIN, SMAX, UMIN, UMAX, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h360 SMIN, SMAX, UMIN, UMAX, enumerator
/external/virglrenderer/src/gallium/auxiliary/tgsi/
Dtgsi_opcode_tmp.h169 OP12(UMIN)
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dminmax-fold.ll434 ; (X <u C1) ? C1 : UMIN(X, C2) ==> UMAX(UMIN(X, C2), C1)
451 ; (X >u C1) ? C1 : UMAX(X, C2) ==> UMIN(UMAX(X, C2), C1)
468 ; (X >u C1) ? UMIN(X, C2) : C1 ==> UMAX(UMIN(X, C2), C1)
485 ; (X <u C1) ? UMAX(X, C2) : C1 ==> UMIN(UMAX(X, C2), C1)
Dxor.ll698 ; CHECK-NEXT: [[UMIN:%.*]] = xor i32 [[UMAX]], -1
700 ; CHECK-NEXT: [[RES:%.*]] = mul i32 [[ADD]], [[UMIN]]
/external/mesa3d/src/broadcom/compiler/
Dv3d_compiler.h823 VIR_A_ALU2(UMIN) in VIR_A_ALU2()
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp209 case ISD::UMIN: return "umin"; in getOperationName()
DLegalizeIntegerTypes.cpp80 case ISD::UMIN: in PromoteIntegerResult()
1381 case ISD::UMIN: in ExpandIntegerResult()
1685 return std::make_pair(ISD::SETLT, ISD::UMIN); in getExpandedMinMaxOps()
1686 case ISD::UMIN: in getExpandedMinMaxOps()
1687 return std::make_pair(ISD::SETULT, ISD::UMIN); in getExpandedMinMaxOps()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp249 case ISD::UMIN: return "umin"; in getOperationName()
/external/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp227 setTargetDAGCombine(ISD::UMIN); in SITargetLowering()
2703 case ISD::UMIN: in minMaxOpcToMin3Max3Opc()
2810 if (Opc == ISD::UMIN && Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) { in performMinMaxCombine()
2873 case ISD::UMIN: in PerformDAGCombine()

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